Resistance change memory

ABSTRACT

A resistance change memory includes a first conductive line extending in a first direction, a second conductive line extending in a second direction which is crossed to the first direction, a cell unit including a memory element and a rectifying element connected in series between the first and second conductive lines, and a control circuit which is connected to both of the first and second conductive lines. The control circuit controls a voltage to change a resistance of the memory element between first and second values reversibly. The rectifying element is a diode including an anode layer, a cathode layer and an insulating layer therebetween.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromprior Japanese Patent Application No. 2009-141427, filed Jun. 12, 2009,the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a resistance change memory having avariable resistive element or a phase-change element as a memoryelement.

2. Description of the Related Art

Recently, resistance change memories such as ReRAM (Resistive RAM) witha variable resistive element as a memory element and PCRAM (Phase changeRAM) with a phase-change element as a memory element are attractingattention as a next-generation nonvolatile semiconductor memory.

Several features of the resistance change memories include (1) a memorycell array of a cross-point type, (2) a large memory capacity realizedby three-dimensional integration, and (3) DRAM-like high-speedoperation.

When the resistance change memory is put to practical use, for example,the NAND flash memory as a file memory and DRAM as a work memory can bereplaced by the resistance change memory.

However, there are many problems to be solved in putting the resistancechange memory to practical use. One of the problems is a characteristicand a thickness of a rectifying element necessary for the cross-pointtype memory cell array.

In the cross-point type memory cell array, the memory element and therectifying element are connected in series between a word line and a bitline (for example, see Jpn. Pat. Appln. KOKAI Publication Nos.2005-136425, 2001-236781, 2008-282499, 2007-311772, and 2008-311663).

A large current during application of a forward bias, a small currentduring application of a reverse bias, and a large breakdown voltage arerequired for the characteristic of the rectifying element in order tocorrectly perform the set/reset operation and the read operation.

In order to satisfy the requirements, it is necessary to increase thethickness of the rectifying element. When the thickness of therectifying element increases, an aspect ratio of a trench formed afterthe processing of the rectifying element becomes large, which isdisadvantageous as regards three-dimensional integration of memory cellarrays.

BRIEF SUMMARY OF THE INVENTION

A resistance change memory according to an aspect of the presentinvention comprises a first conductive line extending in a firstdirection, a second conductive line extending in a second directionwhich is crossed to the first direction, a cell unit including a memoryelement and a rectifying element connected in series between the firstand second conductive lines, and a control circuit which is connected toboth of the first and second conductive lines, wherein the controlcircuit controls a voltage to change a resistance of the memory elementbetween first and second values reversibly, wherein the rectifyingelement is a diode including an anode layer, a cathode layer and aninsulating layer therebetween.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

FIG. 1 illustrates a resistance change memory according to an embodimentof the invention;

FIG. 2 illustrates a cross-point type memory cell array;

FIG. 3 illustrates a cell unit;

FIGS. 4 and 5 illustrate connection relationships between a memoryelement and a rectifying element;

FIGS. 6 to 8 illustrate layouts of first and second control circuits;

FIG. 9 illustrates an operation of the resistance change memory;

FIG. 10 illustrates a device structure of a p-i-n diode;

FIG. 11 illustrates a device structure of an SIS diode;

FIGS. 12 and 13 illustrate a band structure;

FIGS. 14 and 15 illustrate an operation during a forward bias;

FIG. 16 illustrates an operation during a reverse bias;

FIG. 17 illustrates a relationship between a bias and a current value;

FIG. 18 illustrates an embodiment;

FIGS. 19 to 21 illustrate modifications;

FIG. 22 illustrates a device structure of an MIS diode;

FIGS. 23 and 24 illustrate a band structure;

FIGS. 25 and 26 illustrate an operation during a forward bias;

FIG. 27 illustrates an operation during a reverse bias;

FIG. 28 illustrates a device structure of an MIS diode;

FIG. 29 illustrates an effective work function of metal;

FIG. 30 illustrates an embodiment;

FIG. 31 illustrates a modification;

FIG. 32 illustrates an embodiment;

FIG. 33 illustrates a modification;

FIG. 34 illustrates a device structure of an SMIS diode;

FIGS. 35 and 36 illustrate a band structure;

FIGS. 37 and 38 illustrate an operation during a forward bias;

FIG. 39 illustrates an operation during a reverse bias;

FIG. 40 illustrates a device structure of an SMIS diode;

FIG. 41 illustrates a relationship between a bias and a current value;

FIG. 42 illustrates an embodiment;

FIG. 43 illustrates a modification;

FIG. 44 illustrates an embodiment;

FIG. 45 illustrates a modification;

FIG. 46 illustrates a device structure of an MIM diode;

FIG. 47 illustrates a band structure;

FIG. 48 illustrates an operation during a forward bias;

FIG. 49 illustrates an operation during a reverse bias;

FIG. 50 illustrates a device structure of an MIM diode;

FIG. 51 illustrates a band structure;

FIG. 52 illustrates an operation during a forward bias;

FIG. 53 illustrates an operation during a reverse bias; and

FIG. 54 illustrates an embodiment.

DETAILED DESCRIPTION OF THE INVENTION

A resistance change memory of an aspect of the present invention will bedescribed below in detail with reference to the accompanying drawings.

1. BASIC CONCEPT

The present invention is applied to a resistance change memory in whicha memory element is a variable resistive element or a phase-changeelement. The variable resistive element means an element that is made ofa material whose resistance value is changed by a voltage, a current, aheat, or the like. The phase-change element means an element that ismade of a material whose physical property such as a resistance and acapacitance is changed by a phase change.

The term phase change (phase transition) embraces the followingmeanings.

A: Metal-semiconductor transition, metal-insulator transition,metal-metal transition, insulator-insulator transition,insulator-semiconductor transition, insulator-metal transition,semiconductor-semiconductor transition, semiconductor-metal transition,and semiconductor-insulator transition

B: Phase change of quantum states (such as metal-superconductortransition)

C: Paramagnetic-ferromagnetic transition, antiferromagnetic-ferromagnetic transition, ferromagnetic-ferromagnetictransition, ferrimagnetic-ferromagnetic transition, and transition of acombination thereof.

D: Paraelectric-ferroelectric transition, paraelectric-collectortransition, paraelectric-piezoelectric transition,ferroelectric-ferroelectric transition, anti ferroelectric-ferroelectrictransition, and transition of a combination thereof.

E: Transition of a combination of at least two of A to D

Examples of such phase-changing are a transition from a metal, aninsulator, semiconductor, a ferroelectric material, a paraelectricmaterial, a collector, a piezoelectric material, a ferromagneticmaterial, a ferrimagnetic material, a helimagnetic material, aparamagnetic material, or an antiferromagnetic material to aferroelectric-ferromagnetic material, and a reverse transition thereof.

In accordance with the above definition, a variable resistive elementincludes a phase-change element. However, in the embodiment, thevariable resistive element mainly refers to an element made of a metaloxide, a metal compound, an organic thin film, carbon, carbon nanotube,and the like.

The invention is applied to resistance change memories such as ReRAMwith the variable resistive element as the memory element and PCRAM withthe phase-change element as the memory element. This is because theresistance change memories which is a cross-point type memory cell arraysuch as the three-dimensional integration have a DRAM-like high-speedoperation and a large memory capacity.

In a cross-point type memory cell array, the memory element and therectifying element are connected in series between the word line and thebit line in order to pass a current only through the selected memoryelement.

Examples of methods for changing a resistance value of the memoryelement include a method in which the resistance value of the memoryelement is reversibly changed between at least a first value and asecond value by changing a polarity of a voltage applied to the memoryelement, and a method in which the resistance value of the memoryelement is reversibly changed between at least a first value and asecond value by controlling the value and time of a voltage applied tothe memory element without changing the polarity of the voltage.

The former is called a bipolar operation, and the latter is called aunipolar operation.

In the resistance change memory operating by the bipolar operation, itis preferable that the forward bias characteristics and the reverse biascharacteristics of the rectifying element approximate to a line-symmetryto a current axis of I-V characteristics. Therefore, A diode with a MIMstructure or a SIS structure, or a transistor with a bipolar transistorstructure is used as the rectifying element.

For example, the bipolar operation is adopted in memories, such as amagnetic random access memory, in which a bi-directional current isrequired in writing the data. It is possible to apply the bipolaroperation to the resistance change memory of the invention.

The resistance change memory of the invention will be described usingthe unipolar operation in which the resistance value of the memoryelement is reversibly changed between at least the first value and thesecond value by controlling the value and time of the voltage applied tothe memory element without changing the polarity of the voltage.

A large current during the application of the forward bias, a smallcurrent during the application of the reverse bias, and a largebreakdown voltage are required as characteristics of a rectifyingelement in order to correctly perform the set/reset operation and theread operation, when the unipolar operation is applied to the resistancechange memory (hereinafter referred to as cross-point type resistancechange memory) comprising the cross-point type memory cell array.

However, for example, when the rectifying element is formed by a p-njunction diode or a p-i-n diode, it is necessary to increase thethickness of the rectifying element in order to satisfy the aboverequirements. When the thickness of the rectifying element increases,the aspect ratio of the trench formed after the processing of therectifying element becomes large, which is disadvantageous asthree-dimensional integration of memory cell arrays.

As used herein, the p-n junction diode means a diode that has a p-njunction and comprises a p-type semiconductor layer (anode layer) and ann-type semiconductor layer (cathode layer). The p-i-n diode means adiode in which an intrinsic semiconductor layer is provided between thep-type semiconductor layer (anode layer) and the n-type semiconductorlayer (cathode layer).

Therefore, in the embodiment, the rectifying element comprises the anodelayer, the cathode layer, and an insulating layer disposed therebetweenin order that the rectifying element thickness decrease sufficientlywhile the rectifying element characteristic is satisfied for theresistance change memory.

Specifically the rectifying element comprises the following diode:

-   -   SIS (Semiconductor-Insulator-Semiconductor) diode

The SIS diode has a stacked structure of a p-type semiconductor layer(anode layer), insulating layer, and n-type semiconductor layer (cathodelayer).

-   -   MIS (Metal-Insulator-Semiconductor) diode

First, the MIS diode has a stacked structure of a metallic layer (anodelayer), insulating layer, and n-type semiconductor layer (cathodelayer).

Second, the MIS diode has a stacked structure of a metallic layer(cathode layer), insulating layer, and p-type semiconductor layer (anodelayer).

-   -   SMIS (Semiconductor-Metal-Insulator-Semiconductor) diode

The SMIS diode includes all the elements of the MIS diode, the SMISdiode is categorized as an MIS diode.

First, the SMIS diode has a stacked structure of a p-type semiconductorlayer (anode layer), metallic layer (anode layer), and insulatinglayer-n-type semiconductor layer (cathode layer).

Second, the SMIS diode has a stacked structure of an n-typesemiconductor layer (cathode layer), metallic layer (cathode layer),insulating layer, and p-type semiconductor layer (anode layer.

-   -   MIM (Metal-Insulator-Metal) diode

The MIM diode has a stacked structure of a metallic layer (anode layer),insulating layer, and metallic layer (cathode layer).

When these diodes are used as a rectifying element for a cross-pointtype resistance change memory, a decrease in film thickness of therectifying element, which is satisfied for three-dimensional integrationof the memory cell array, and maintenance or improvement of a rectifyingcharacteristic of the rectifying element can be achieved in a generationwhose minimum line width is 30 nm or less.

An operation mechanism and an effect of the use of each diode will bedescribed in detail in the following embodiments.

2. EMBODIMENTS

(1) Overall View

FIG. 1 illustrates a main part of a resistance change memory accordingto an embodiment of the invention.

Resistance change memory (for example, chip) 1 comprises cross-pointtype memory cell array 2. Cross-point type memory cell array 2 has astacked structure of memory cell arrays.

First control circuit 3 is disposed at one end in a first direction ofcross-point type memory cell array 2, and second control circuit 4 isdisposed at one end in a second direction intersecting the firstdirection.

For example, first and second control circuits 3 and 4 select one ofstacked memory cell arrays based on a memory cell array selectionsignal.

For example, first control circuit 3 selects a row of cross-point typememory cell array 2 based on a row address signal. For example, secondcontrol circuit 4 selects a column of cross-point type memory cell array2 based on a column address signal.

First and second control circuits 3 and 4 control datawrite/erasing/read with respect to a memory element in cross-point typememory cell array 2.

First and second control circuits 3 and 4 can perform the datawrite/erasing/read with respect to one of the stacked memory cellarrays, and can simultaneously perform the data write/erasing/read withrespect to at least two or all the stacked memory cell arrays.

As used herein, in resistance change memory 1, the write is referred toas set and the erasing is referred to as reset. It is necessary for aresistance value in the set state to differ from a resistance value inthe reset state, and it does not matter whether the resistance value inthe set state is higher or lower than the resistance value in the resetstate.

A multi-level resistance change memory in which multi-level data isstored in one memory element can be implemented when one of theresistance values is selectively written during the set operation.

Controller (host) 5 supplies a control signal and data to resistancechange memory 1. The control signal is fed into command interfacecircuit 6, and the data is fed into data input/output buffer 7. Thecontroller 5 may be disposed in chip 1, or in a host (computer) that isdifferent from chip 1.

Command interface circuit 6 determines whether the data from host 5 iscommand data based on the control signal. When the data from host 5 iscommand data, command interface circuit 6 transfers the data to statemachine 8 from data input/output buffer 7.

State machine 8 manages an operation of resistance change memory 1 basedon the command data. For example, state machine 8 manages a set/resetoperation and a read operation based on the command data from host 5.

Controller 5 can also determine an operation result in resistance changememory 1 by receiving status information managed by state machine 8.

In the set/reset operation and the read operation, controller 5 suppliesan address signal to resistance change memory 1. For example, theaddress signal includes the memory cell array selection signal, the rowaddress signal, and the column address signal.

The address signal is fed into first and second control circuits 3 and 4through address buffer 9.

In response to a command from state machine 8, pulse generator 10outputs a voltage pulse or a current pulse necessary for the set/resetoperation and the read operation at a predetermined timing.

(2) Memory Cell Array

FIG. 2 illustrates a cross-point type memory cell array.

Cross-point type memory cell array 2 is disposed on semiconductorsubstrate (for example, silicon substrate) 11. A circuit element such asa MOS transistor or an insulating film may be sandwiched betweencross-point type memory cell array 2 and semiconductor substrate 11.

In FIG. 2, cross-point type memory cell array 2 comprises four memorycell arrays, M1, M2, M3, and M4 stacked in a third direction (directionperpendicular to a principal surface of semiconductor substrate 11) byway of example, and it is necessary that at least two memory cell arraysbe stacked.

Memory cell array M1 comprises cell units CU1 that are arrayed in thefirst and second directions.

Similarly, memory cell array M2 comprises arrayed cell units CU2, memorycell array M3 comprises arrayed cell units CU3, and memory cell array M4comprises arrayed cell units CU4.

Each of cell units CU1, CU2, CU3, and CU4 comprises a memory element anda rectifying element, which are connected in series.

Conductive lines L1(j−1), L1(j), and L1(j+1), conductive lines L2(i−1),L2(i), and L2(i+1), conductive lines L3(j−1), L3(j), and L3(j+1),conductive lines L4(i−1), L4(i), and L4(i+1), and conductive linesL5(j−1), L5(j), and L5(j+1) are disposed on semiconductor substrate 11.

The odd-numbered conductive lines, that is, conductive lines L1(j−1),L1(j), and L1(j+1), conductive lines L3(j−1), L3(j), and L3(j+1), andconductive lines L5(j−1), L5(j), and L5(j+1) are extended toward thesecond direction from the side of semiconductor substrate 11.

The even-numbered conductive lines, that is, conductive lines L2(i−1),L2(i), and L2(i+1) and conductive lines L4(i−1), L4(i), and L4(i+1) areextended toward the first direction from the side of semiconductorsubstrate 11.

The conductive lines act as a word line or a bit line.

Lowermost first memory cell array M1 is disposed between firstconductive lines L1(j−1), L1(j), and L1(j+1) and second conductive linesL2(i−1), L2(i), and L2(i+1). In the set/reset operation and the readoperation to memory cell array M1, one of conductive lines L1(j−1),L1(j), and L1(j+1) and conductive lines L2(i−1), L2(i), and L2(i+1) actsas the word line, and the other acts as the bit line.

Memory cell array M2 is disposed between second conductive linesL2(i−1), L2(i), and L2(i+1) and third conductive lines L3(j−1), L3(j),and L3(j+1). In the set/reset operation and the read operation to memorycell array M2, one of conductive lines L2(i−1), L2(i), and L2(i+1) andconductive lines L3(j−1), L3(j), and L3(j+1) acts as the word line, andthe other acts as the bit line.

Memory cell array M3 is disposed between third conductive lines L3(j−1),L3(j), and L3(j+1) and fourth conductive lines L4(i−1), L4(i), andL4(i+1). In the set/reset operation and the read operation to memorycell array M3, one of conductive lines L3(j−1), L3(j), and L3(j+1) andconductive lines L4(i−1), L4(i), and L4(i+1) acts as the word line, andthe other acts as the bit line.

Memory cell array M4 is disposed between fourth conductive linesL4(i−1), L4(i), and L4(i+1) and fifth conductive lines L5(j−1), L5(1),and L5(j+1). In the set/reset operation and the read operation to memorycell array M4, one of the conductive lines L4(i−1), L4(i), and L4(i+1)and conductive lines L5(j−1), L5(j), and L5(j+1) acts as the word line,and the other acts as the bit line.

(3) Cell Unit

FIG. 3 illustrates a cell unit in two memory cell arrays.

FIG. 3 illustrates, for example, cell units CU1 and CU2 in memory cellarrays M1 and M2 of FIG. 2. At this point, configurations of the cellunits in memory cell arrays M3 and M4 of FIG. 2 are similar to those ofthe cell units of memory cell arrays M1 and M2 of FIG. 2.

Each of cell units CU1 and CU2 comprises the memory element and therectifying element, which are connected in series.

There are various patterns in a connection relationship between thememory element and the rectifying element.

However, it is necessary that the connection relationships between thememory element and the rectifying element be identical to one another inall the cell units of one memory cell array.

FIGS. 4 and 5 illustrate connection relationships between the memoryelement and the rectifying element.

In one cell unit, a total of 4 ways exist in the connection relationshipbetween the memory element and the rectifying element, that is, 2 waysexist in a positional relationship between the memory element and therectifying element and 2 ways exist in an orientation of the rectifyingelement. Accordingly, for the cell units of the two memory cell arrays,patterns of 16 ways (4 ways×4 ways) exist in the connection relationshipbetween the memory element and the rectifying element.

In FIGS. 4 and 5, the letters (a) to (p) designate the connectionrelationship of 16 ways.

In cell units CU1 and CU2, the lower side of the drawings is thesemiconductor substrate side.

Although the embodiment can be applied to all the connectionrelationship of 16 ways, the connection relationship (c) will mainly bedescribed below by way of example.

This is because that two cell units being adjacent to each other canshare a conductive line L as a common word line or a common bit line,when the diodes in the two cell units are arranged symmetrically to theconductive line L. As a result, the operation of the resistance changememory is easily controlled.

(4) Layout of First and Second Control Circuits

FIGS. 6 and 7 illustrate a first example of a layout of the first andsecond control circuits.

Memory cell array Ms corresponding to one of the layers of memory cellarrays M1, M2, M3, and M4 of FIG. 2 comprises cell units CUs arrayed asillustrated in FIG. 6. One end of cell unit CUs is connected toconductive lines Ls(j−1), Ls(j), and Ls(j+1), and the other end isconnected to conductive lines Ls+1(i−1), Ls+1(i), and Ls+1(i+1).

As illustrated in FIG. 7, memory cell array Ms+1 comprises arrayed cellunits CUs+1. One end of cell unit CUs+1 is connected to conductive linesLs+1(i−1), Ls+1(i), and Ls+1(i+1), and the other end is connected toconductive lines Ls+2(j−1), Ls+2(j), and Ls+2(j+1).

Where s is 1, 3, 5, 7, . . . .

First control circuit 3 is connected to one end in the first directionof each of conductive lines Ls+1(i−1), Ls+1(i), and Ls+1(i+1) throughswitch element SW1. For example, switch circuit SW1 comprises anN-channel FET (Field Effect Transistor) that is controlled by controlsignals φs+1(i−1), φs+1(i), and φs+1(i+1).

Second control circuit 4 is connected to one end in the second directionof each of conductive lines Ls(j−1), Ls(j), and Ls(j+1) through switchelement SW2. For example, switch circuit SW2 comprises the N-channel FETthat is controlled by control signals φs(j−1), φs(j), and φs(j+1).

Second control circuit 4 is connected to one end in the second directionof each of the conductive lines Ls+2(j−1), Ls+2(j), and Ls+2(j+1)through switch element SW2. For example, switch circuit SW2 comprisesthe N-channel FET that is controlled by control signals φs+2(j−1),φs+2(j), and φs+2(j+1).

FIG. 8 illustrates a second example of a layout of the first and secondcontrol circuits.

The layout of the second example differs from the layout of the firstexample in that first control circuits 3 are disposed at both ends inthe first direction of each of the memory cell arrays Ms, Ms+1, Ms+2,and Ms+3 while second control circuits 4 are disposed at both ends inthe second direction of each of the memory cell arrays Ms, Ms+1, Ms+2,and Ms+3.

Where s is 1, 5, 9, 13, . . . .

First control circuits 3 are connected to both ends in the firstdirection of each of conductive lines Ls+1(i−1), Ls+1(i), and Ls+1(i+1)through switch elements SW1. For example, switch circuit SW1 comprisesthe N-channel FET that is controlled by control signals φs+1(i−1),φs+1(i), φs+1(i+1), φs+3(i−1), φs+3(i), and φs+3(i+1).

Second control circuits 4 are connected to both ends in the seconddirection of each of conductive lines Ls(j−1), Ls(j), and Ls(j+1)through switch elements SW2. For example, switch circuit SW2 comprisesthe N-channel FET that is controlled by control signals φs(j−1), φs(j),φs(j+1), φs+2(j−1), φs+2(j), and φs+2(j+1).

(5) Operation

An operation of the resistance change memory will be described.

FIG. 9 illustrates two memory cell arrays.

Memory cell array M1 of FIG. 9 corresponds to the memory cell array M1of FIG. 2, and memory cell array M2 of FIG. 9 corresponds to memory cellarray M2 of FIG. 2.

The connection relationship between the memory element and therectifying element in cell units CU1 and CU2 corresponds to connectionrelationship (c) of FIG. 4.

A. Set Operation

A write (set) operation performed to selected cell unit CU1-sel inmemory cell array M1 will be described.

An initial state of selected cell unit CU1-sel is an erasing (reset)state.

It is assumed that the reset state is a high-resistance state (100 kΩ to1 MΩ) while the set state is a low-resistance state (1 KΩ to 10 KΩ).

Selected conductive line L2(i) is connected to high-potential-side powersupply potential Vdd, and selected conductive line L1(j) is connected tolow-potential-side power supply potential Vss.

In the first conductive lines from the semiconductor substrate side,non-selected conductive lines L1(j−1) and L1(j+1) other than selectedconductive line L1(j) are connected to power supply potential Vdd. Inthe second conductive lines from the semiconductor substrate side,non-selected conductive line L2(i+1) other than selected conductive lineL2(i) is connected to power supply potential Vss.

Third non-selected conductive lines L3(j−1), L3(j), and L3(j+1) from thesemiconductor substrate side are connected to power supply potentialVdd.

At this point, because the forward bias is applied to the rectifyingelement (diode) in selected cell unit CU1-sel, set current I-set ispassed from a constant current source to selected cell unit CU1-sel, andthe resistance value of the memory element in selected cell unit CU1-selchanges from the high-resistance state to the low-resistance state.

In the set operation, a voltage of 1 to 2 V is applied to the memoryelement in selected cell unit CU1-sel, and the current density of setcurrent I-set passed through the memory element (high-resistance state)is set to a range of 1×10⁵ to 1×10⁷ A/cm².

On the other hand, in non-selected cell units CU1-unsel in memory cellarray M1, the reverse bias is applied to the rectifying element (diode)in the cell unit, which is connected between non-selected conductivelines L1(j−1) and L1(j+1) and non-selected conductive line L2(i+1).

Similarly, in non-selected cell units CU2-unsel in memory cell array M2,the reverse bias is applied to the rectifying element (diode) in thecell unit, which is connected between non-selected conductive lineL2(i+1) and non-selected conductive lines L3(j−1), L3(j), and L3(j+1).

Accordingly, a sufficiently small current during the application of thereverse bias and sufficiently large breakdown voltage are required forthe characteristic of the rectifying element in the cell unit.

B. Reset Operation

An erasing (reset) operation performed to selected cell unit CU1-sel inmemory cell array M1 will be described.

Selected conductive line L2(i) is connected to high-potential-side powersupply potential Vdd, and selected conductive line L1(j) is connected tolow-potential-side power supply potential Vss.

In first conductive lines from the semiconductor substrate side,non-selected conductive lines L1(j−1) and L1(j+1) other than selectedconductive line L1(j) are connected to power supply potential Vdd. Inthe second conductive lines from the semiconductor substrate side,non-selected conductive line L2(i+1) other than selected conductive lineL2(i) is connected to power supply potential Vss.

Third non-selected conductive lines L3(j−1), L3(j), and L3(j+1) from thesemiconductor substrate side are connected to power supply potentialVdd.

At this point, because the forward bias is applied to the rectifyingelement (diode) in selected cell unit CU1-sel, reset current I-reset ispassed from the constant current source to selected cell unit CU1-sel,and the resistance value of the memory element in selected cell unitCU1-sel changes from the low-resistance state to the high-resistancestate.

In the reset operation, the voltage of 1 to 3 V is applied to the memoryelement in selected cell unit CU1-sel, and the current density of resetcurrent 1-reset passed through the memory element (low-resistance state)is set to a range of 1×10³ to 1×10⁶ A/cm².

On the other hand, in non-selected cell units CU1-unsel in memory cellarray M1, the reverse bias is applied to the rectifying element (diode)in the cell unit, which is connected between non-selected conductivelines L1(j−1) and L1(j+1) and non-selected conductive line L2(i+1).

Similarly, in non-selected cell units CU2-unsel in memory cell array M2,the reverse bias is applied to the rectifying element (diode) in thecell unit, which is connected between non-selected conductive lineL2(i+1) and non-selected conductive lines L3(j−1), L3(j), and L3(j+1).

Accordingly, a sufficiently small current during the application of thereverse bias and sufficiently large breakdown voltage are required forthe characteristic of the rectifying element in the cell unit.

Set current I-set and reset current I-reset differ from each other. Thevoltage applied to the memory element in selected cell unit CU1-sel inorder to produce set current I-set and reset current I-reset depends ona material for the memory element.

C. Read Operation

A read operation performed to selected cell unit CU1-sel in memory cellarray M1 will be described.

Selected conductive line L2(i) is connected to high-potential-side powersupply potential Vdd, and selected conductive line L1(j) is connected tolow-potential-side power supply potential Vss.

In first conductive lines from the semiconductor substrate side,non-selected conductive lines L1(j−1) and L1(j+1) other than selectedconductive line L1(j) are connected to power supply potential Vdd. Inthe second conductive lines from the semiconductor substrate side,non-selected conductive line L2(i+1) other than selected conductive lineL2(i) is connected to power supply potential Vss.

Third non-selected conductive lines L3(j−1), L3(j), and L3(j+1) from thesemiconductor substrate side are connected to power supply potentialVdd.

At this point, because the forward bias is applied to the rectifyingelement (diode) in selected cell unit CU1-sel, read current I-read ispassed from the constant current source to the memory element(high-resistance state or low-resistance state) in selected cell unitCU1-sel.

Accordingly, for example, the data (resistance value) of the memoryelement can be read by detecting a potential change at a sense node inpassing read current I-read through the memory element.

At this point, it is necessary that read current I-read be sufficientlysmaller than set current I-set and reset current I-reset such that theresistance value of the memory element does not change during the readoperation.

As with the set/reset operation, during the read operation, the reversebias is applied to the rectifying element (diode) in the cell unit whichis connected between non-selected conductive lines L1(j−1) and L1(j+1)and non-selected conductive line L2(i+1), in non-selected cell unitsCU1-unsel in memory cell array M1.

Similarly, in non-selected cell units CU2-unsel in memory cell array M2,the reverse bias is applied to the rectifying element (diode) in thecell unit which is connected between non-selected conductive lineL2(i+1) and non-selected conductive lines L3(j−1), L3(j), and L3(j+1).

Accordingly, a sufficiently small current during the application of thereverse bias and sufficiently large breakdown voltage are required forthe characteristic of the rectifying element in the cell unit.

(6) Rectifying Element

The rectifying element (non-ohmic element) used in the resistance changememory of the embodiment will be described in detail. The connectionrelationship between the memory element and the rectifying element inthe cell unit is shown in (c) of FIG. 4.

A. P-i-n diode

The p-i-n diode will briefly be described as a comparative example.

FIG. 10 illustrates a structure of the p-i-n diode.

Electrode layer 12, n-type semiconductor layer 13, intrinsicsemiconductor layer 14, p-type semiconductor layer 15, and electrodelayer 16 are stacked on conductive line L2(i) extended in the firstdirection. Intrinsic semiconductor layer 14 is a semiconductor layer inwhich an impurity is not doped or a semiconductor layer that contains anegligible trace of impurity with respect to intrinsic carrier density.

P-i-n diode D-pin comprises n-type semiconductor layer 13, intrinsicsemiconductor layer 14, and p-type semiconductor layer 15.

Memory element 17, which is the variable resistive element or thephase-change element, and electrode layer 18 are stacked on electrodelayer 16. Conductive line L3(j) is disposed on electrode layer 18, andextended in the second direction intersecting the first direction.

In p-i-n diode D-pin, in order to realize the set/reset operation, thereverse current of the p-i-n diode should be suppressed sufficiently incase of the reverse bias is applied during the set/rest operation.

Therefore, the thickness in the third direction of p-i-n diode D-pin isset to a range of 100 nm to 200 nm. For example, n-type semiconductorlayer 13 is set to 15 nm, intrinsic semiconductor layer 14 is set to 120nm, p-type semiconductor layer 15 is set to 15 nm, and the thickness ofp-i-n diode D-pin is set to 150 nm.

However, in case of the resistance change memory, which is anext-generation memory, is manufactured by a rule of minimum line widthof 30 nm or less, although a width of the trench formed after theprocessing of the rectifying element becomes 30 nm or less, a height ofthe trench (included the thickness of the memory element and electrodelayer) exceeds 100 nm.

Therefore, the aspect ratio of the trench increases, which isdisadvantageous as regards three-dimensional integration of cross-pointtype memory cell arrays.

For example, when the resistance change memory is manufactured by a ruleof minimum line width of 30 nm or less, the thickness of the rectifyingelement (non-ohmic element) should be 100 nm or less in order to realizethree-dimensional integration of the cross-point type memory cell array.

The following rectifying element realizes three-dimensional integrationof the cross-point type memory cell array.

B. SIS Diode

(a) Structure

FIG. 11 illustrates a structure of an SIS diode. SIS diode D-sis has astacked structure of n-type semiconductor layer 13, insulating layer 21,and p-type semiconductor layer 15.

SIS diode D-sis is disposed on electrode layer 12, electrode layer 16 isdisposed on SIS diode D-sis, memory element 17 is the variable resistiveelement (ReRAM) or the phase-change element (PCRAM) is disposed onelectrode layer 16, and electrode layer 18 is disposed on memory element17.

The positional relationship between the memory element and therectifying element and the structures of the memory element and therectifying element may be changed in various ways as long as therectifying characteristic of the rectifying element is not lost. Forexample, the memory element and the rectifying element may be formedupside down, the cathode and anode of the rectifying element may bereversed, the electrode layer may be omitted or added, a barrier layerthat suppresses diffusion of the impurity may be added, or a combinationthereof may be performed.

A memory function of utilizing an insulating characteristic changecaused by a trap or ion movement may be added to the insulating layerconstituting the SIS diode.

One of the features of SIS diode D-sis is that the reverse currentcaused by the reverse bias can be sufficiently suppressed during theset/reset operation even if the thickness in the third direction of SISdiode D-sis is set to 100 nm or less.

For example, the thickness in the third direction of SIS diode D-sis isset to a range of 25 nm to 100 nm. For example, n-type semiconductorlayer 13 is set to 15 nm, insulating layer 21 is set to 1 nm, and p-typesemiconductor layer 15 is set to 15 nm, thereby setting the thickness ofSIS diode D-sis to 31 nm.

The thickness of insulating layer 21 is determined based on thecondition that a charge tunneling phenomenon (including both directtunneling and FN (Fowler-Noldheim) tunneling) is generated betweenn-type semiconductor layer 13 and p-type semiconductor layer 15.

For example, when insulating layer 21 is made of SiO₂, the thickness ofinsulating layer 21 is set to a range of 0.1 to 3 nm. When insulatinglayer 21 is made of SiN or Al₂O₃, the thickness of insulating layer 21is set to a range of 0.1 to 3 nm.

Insulating layer 21 may include an impurity atom or asemiconductor/metal dot (quantum dot), which forms a defect level. Afine rectifying element (non-ohmic element) that can be formed at a lowtemperature can be shrunk by the above structure.

Insulating layer 21 may be formed by a single layer or plural layers. Incase of insulating layer 21 is formed by plural layers, preferably thelayers have different barrier heights or different permittivities.

For example, it is assumed that insulating layer 21 is formed byinsulating layers 21A and 21B having different barrier heights. Forexample, the insulating layer 21A is made of SiO₂ having a thickness of0.5 nm while insulating layer 21B is made of TiO₂ having a thickness of1 nm. In such cases, in case of a bias is not applied, the barrierheight of insulating layer 21A is higher than that of insulating layer21B.

In case of the forward bias is applied to the SIS diode, becauseelectrons are only influenced by the thickness of insulating layer 21A,the charge movement is generated by the FN tunneling of insulating layer21A, and the current passed through the SIS diode increases withincreasing forward bias.

On the other hand, in case of the reverse bias is applied to the SISdiode, because electrons are influenced by the sum of thickness ofinsulating layers 21A and 21B, the charge is not tunneling throughinsulating layers 21A and 21B, and the current is not passed through theSIS diode.

For this example, the reverse current of the SIS diode can besufficiently suppressed against the reverse bias. At the same time, asufficiently large forward current (set/reset current) can be obtainedwith respect to the forward bias.

(b) Operation Mechanism

An operation mechanism of the SIS diode will be described.

FIGS. 12 to 13 illustrate a band structure of the SIS diode.

In case of the insulating layer is disposed between the p-typesemiconductor layer and the n-type semiconductor layer, the SIS diodehas the structure of FIG. 12 before band modulation, and has thestructure of FIG. 13 after the band modulation.

However, the insulating layer is made of SiO₂ having a thickness of 1nm.

In case of a voltage less than 1 V is applied as the forward bias to theSIS diode, as illustrated in FIG. 14, charge movement is generated bythe direct tunneling of the insulating layer (SiO₂), and the currentpassed through the SIS diode increases with increasing forward bias.

In case of a voltage of 1 V or more is applied as the forward bias tothe SIS diode, as illustrated in FIG. 15, charge movement is generatedby the FN tunneling of the insulating layer (SiO₂), and the currentpassed through the SIS diode increases with increasing forward bias.

On the other hand, In case of a voltage less than 1 V is applied as thereverse bias to the SIS diode, as illustrated in FIG. 16, because therethe carrier is not tunneling through the insulating layer (SiO₂), thecurrent is not passed through the SIS diode.

For this example, the reverse current of the SIS diode can besufficiently suppressed against the reverse bias of 1 V. At the sametime, a sufficiently large forward current (set/reset current) can beobtained with respect to the forward bias of 1 V.

As the insulating layer is further thickened, the reverse biascharacteristic can further be improved. That is, in applying the reversebias, the reverse current decreases while the breakdown voltageincreases as the insulating layer is thickened.

FIG. 17 illustrates a relationship between a bias direction and acurrent value.

The insulating layer is made of SiO₂ having a thickness of 0.5 nm (X ofFIG. 17), 2 nm (Y of FIG. 17), and 3 nm (Z of FIG. 17).

As is clear from FIG. 17, when the insulating layer has a thickness of0.5 nm, the current passed through the SIS diode can be suppressedagainst the reverse bias of about 0.8 V (A point of FIG. 17).

In case of the insulating layer has a thickness of 2 nm, the current isnot passed through the SIS diode against the reverse bias of about 2 V(B point of FIG. 17). When the insulating layer has a thickness of 3 nm,the current passed through the SIS diode can be suppressed against thereverse bias of about 3 V (C point of FIG. 17). It is not necessary thatthe SIS diode be completely turned off in the reverse bias. It is onlynecessary to pass the current through the SIS diode such that a set orreset error, or a read error is not occurred in the non-selected memorycell. Considering this point, the insulating film may have a thicknessof 0.5 nm or less even if the reverse bias of 0.8 V is applied to theSIS diode. Generally, because the reverse bias applied to the diode ofthe resistance change memory ranges from 0.8 V to 3 V (except forforming operation), the thickness of the insulating layer constitutingthe SIS diode ranges from 0.1 to 3 nm as described above.

Specifically, the thickness of the insulating layer is determined inconsideration of the forward bias characteristic.

In case of the thickness of the insulating layer is 1 nm or less (exceptzero), the forward bias characteristics and the reverse biascharacteristics of the SIS diode can be approximate to a line-symmetryto a current axis of 1-V characteristics. In this case, the SIS diodemay include an intrinsic semiconductor layer with 10 nm or less. As aresult, it is possible to apply the bipolar operation to the resistancechange memory.

Although the insulating layer is made of SiO₂ in the example, the sameholds true for an insulating layer made of SiN or Al₂O₃.

(c) Embodiments

FIG. 18 illustrates a structure of the SIS diode.

Electrode layer 12, n-type semiconductor layer 13, insulating layer 21,p-type semiconductor layer 15, and electrode layer 16 are stacked onconductive line L2(i) extended in the first direction. SIS diode D-siscomprises n-type semiconductor layer 13, insulating layer 21, and p-typesemiconductor layer 15.

Memory element 17, which is the variable resistive element or thephase-change element, and electrode layer 18 are stacked on electrodelayer 16. Conductive line L3(j) is disposed on electrode layer 18, andextended in the second direction intersecting the first direction.

In SIS diode D-sis, in order to realize the set/reset operation, thereverse current of the SIS diode should be suppress sufficiently, incase of the reverse bias is applied during the set/reset operation.

Therefore, the thickness of SIS diode D-sis in the third direction isset to a range of 25 nm to 100 nm. For example, n-type semiconductorlayer 13 is set to 15 nm, insulating layer 21 is set to 1 nm, and p-typesemiconductor layer 15 is set to 15 nm, whereby the thickness of SISdiode D-sis becomes 31 nm.

FIGS. 19 to 21 illustrate modifications of the SIS diode of FIG. 18.

The structure of the SIS diodes of the modifications differ from thestructure of the SIS diode of FIG. 18 in that intrinsic semiconductorlayer 22 is provided.

Specifically, in the modification of FIG. 19, intrinsic semiconductorlayer 22 is disposed between n-type semiconductor layer 13 andinsulating layer 21. In the modification of FIG. 20, intrinsicsemiconductor layer 22 is disposed between insulating layer 21 andp-type semiconductor layer 15.

In the modification of FIG. 21, intrinsic semiconductor layers 22 aredisposed between n-type semiconductor layer 13 and insulating layer 21and between insulating layer 21 and p-type semiconductor layer 15.

The addition of intrinsic semiconductor layer 22 can further improve thereverse bias characteristic of the SIS diode. That is, the reverse biascharacteristic can be suppressed within the permissible aspect ratio bythe thickened intrinsic semiconductor layer and the thickened insulatingfilm.

In case of the insulating layer 21 is thickened, the forward current ishardly passed, although the current can be considerably suppressedduring the reverse bias. Therefore, in case of intrinsic semiconductorlayer 22 is added while insulating layer 21 is thinned, the forwardcurrent can be increased, while the current is suppressed during thereverse bias.

(d) Material Example

A concrete example of the resistance change memory in which the SISdiode is used as the rectifying element will be described. The suffix xof WSix indicates any composition ratio.

The p-type semiconductor layer and the n-type semiconductor layer, whichconstitute the SIS diode, are selected from the group of Si, SiGe, SiC,Ge, C, a III-V semiconductor such as GaAs, a II-V1 semiconductor such asZnSe, an oxide semiconductor, a nitride semiconductor, a carbidesemiconductor, and a sulfide semiconductor.

Preferably, the p-type semiconductor layer (anode layer) is one ofp-type Si, TiO₂, ZrO₂, InZnO_(x), ITO, SnO₂ containing Sb, ZnOcontaining Al, AgSbO₃, InGaZnO₄, ZnO.SnO₂, or a combination thereof.

Preferably, the n-type semiconductor layer (cathode layer) is one ofn-type Si, NiO_(x), ZnO, Rh₂O₃, ZnO containing N, La₂CuO₄, or acombination thereof.

For example, the insulating layer constituting the SIS diode is selectedfrom the following materials.

A) Oxide

-   -   SiO₂, Al₂O₃, Y₂O₃, La₂O₃, Gd₂O₃, Ce₂O₃, CeO₂, Ta₂O₅, HfO₂, ZrO₂,        TiO₂, HfSiO, HfAlO, ZrSiO, ZrAlO, AlSiO, or a combination        thereof.    -   AB₂O₄

Where A and B are identical or different elements and one of Al, Sc, Ti,V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, or a combination thereof.

For example, Fe₃O₄, FeAl₂O₄, Mn_(1+x)Al_(2−x)O_(4+y),CO_(1+x)Al_(2−x)O_(4+y), and MnO_(x)

-   -   ABO₃

Where A and B are identical or different elements and one of Ai, La, Hf,Ta, W, Re, Os, Ir, Pt, Au, Hg, Tl, Pb, Bi, Ce, Pr, Nd, Pm, Sm, Eu, Gd,Tb, Dy, Ho, Er, Tm, Yb, Lu, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga,Ge, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, In, Sn, or a combinationthereof.

For example, LaAlO₃, SrHfO₃, SrZrO₃, and SrTiO₃

B) Oxynitride

-   -   SiON, AlON, YON, LaON, GdON, CeON, TaON, HfON, ZrON, TiON,        LaAlON, SrHfON, SrZrON, SrTiON, HfSiON, HfAlON, ZrSiON, ZrAlON,        AlSiON, or a combination thereof.    -   A material replaced some of the oxygen elements of the material        in A) Oxide to a nitrogen element.

Particularly, the insulating layer constituting the SIS diode ispreferably selected from the group of SiO₂, SiN, Si₃N₄, Al₂O₃, SiON,HfO₂, HfSiON, Ta₂O₅, TiO₂, and SrTiO₃.

The insulating layer includes an insulating layer that contains animpurity atom or a semiconductor/metal dot (quantum dot), which forms adefect level.

The conductive line that acts as the word line/bit line is made of W,WN, Al, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, TiN, WSi_(x), TaSi_(x), PdSi_(x),ErSi_(x), YSi_(x), PtSi_(x), HfSi_(x), NiSi_(x), CoSi_(x), TiSi_(x),VSi_(x), CrSi_(x), MhSi_(x), FeSi_(x), or a combination thereof.

A single metal element or a mixture of metal elements, silicide, oxide,and nitride can be cited as an example of the material for the electrodelayer. Specifically, the electrode layer is made of Pt, Au, Ag, TiAlN,SrRuO, Ru, RuN, Ir, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, TiN, TaN, LaNiO, Al,PtIrO_(x), PtRhO_(x), Rh, TaAlN, SiTiO_(x), WSi_(x), TaSi_(x), PdSi_(x),PtSi_(x), IrSi_(x), ErSi_(x), YSi_(x), HfSi_(x), NiSi_(x), CoSi_(x),TiSi_(x), VSi_(x), CrSi_(x), MnSi_(x), FeSi_(x), or a combinationthereof. The electrode layer may simultaneously have a function as abarrier metallic layer or a bonding layer.

For example, the memory element is made of a binary or ternary metaloxide or an organic material (including single-layer film and nanotube).For example, the carbon material includes a single-layer film, nanotube,and a two-dimensional structure such as graphene and fullerene. Themetal oxide includes A) Oxide and B) Oxynitride.

(e) Effect

In case of the SIS diode is used as the rectifying element of theresistance change memory, the thickness of the rectifying element can bedecreased to ½ to ⅓ that of the p-n junction diode and the p-i-n diodewhile the rectifying element has the sufficient rectifyingcharacteristic. In other words, when the SIS diode has the samethickness as the p-n junction diode or the p-i-n diode, the reversecurrent of the SIS diode to which the reverse bias is applied decreases10² or more compared with the p-n junction diode or p-i-n diode, towhich the identical reverse bias is applied.

Accordingly, a reduction of power consumption of the resistance changememory, improvement of operating speed, and ease of read can berealized.

As both the anode layer and cathode layer of the SIS diode are made of asemiconductor, the rectifying characteristic can be controlled bychanging a Fermi level of the semiconductor. Particularly, in theforward bias, the Fermi level of the n-type semiconductor layer on theelectron-injection side is relatively raised, and the Fermi level of thep-type semiconductor layer on the electron-reception side is relativelylowered, which allows an enhancement of the rectifying characteristic.

The SIS diode comprises plural insulating layers, and the insulatinglayers differ from each other in the barrier height or the permittivity.Therefore, an on/off-ratio of the SIS diode can be improved by thedifferent barrier heights or permittivities of the insulating layers andthe impurity concentrations of the p-type semiconductor layer and n-typesemiconductor layer.

The on/off-ratio can also be improved by incorporating a trap level (adot or a defect of the impurity or Si) in the single or pluralinsulating films asymmetrically.

Ultimately, the forward current can be significantly improved by greatlythinning the insulating film. Actually, the current characteristic canbe improved by the use of an extremely-thin insulating film (with athickness of less than 1 nm) made of SiOx, SiNx, TiOx, NiOx, WOx, andthe like, which are formed by natural oxidation or marginal oxidation ornitridation by SPA.

As used herein, the on/off-ratio means a ratio (I-forward/I-reverse) offorward current I-forward and reverse current I-reverse in case of theforward bias is equal to the reverse bias in an absolute value.

C. MIS Diode

(a) Structure

FIG. 22 illustrates a first example of a structure of the MIS diode.

MIS diode D-mis has a stacked structure of a p-type semiconductor layer15, insulating layer 21, and metallic layer 23.

Electrode layer 16 is disposed on MIS diode D-mis, memory element 17which is the variable resistive element (ReRAM) or the phase-changeelement (PCRAM) is disposed on electrode layer 16, and electrode layer18 is disposed on memory element 17.

The positional relationship between the memory element and therectifying element and the structures of the memory element and therectifying element may be changed in various ways as long as therectifying characteristic of the rectifying element is not lost.

For example, the memory element and the rectifying element may be formedupside down, the cathode and anode of the rectifying element may bereversed, the electrode layer may be omitted or added, a barrier layerthat suppresses diffusion of the impurity may be added, and acombination thereof may be performed.

The memory function of utilizing the insulating characteristic changecaused by a trap or ion movement may be added to the insulating layerconstituting the MIS diode.

One of the features of MIS diode D-mis is that the reverse currentcaused by the reverse bias can be sufficiently suppressed during theset/reset operation even if the thickness in the third direction of MISdiode D-mis is set to 100 nm or less.

For example, the thickness in the third direction of MIS diode D-mis isset to the range of 25 nm to 100 nm. For example, p-type semiconductorlayer 15 is set to 15 nm, insulating layer 21 is set to 1 nm, andmetallic layer 23 is set to 10 nm, whereby the thickness of MIS diodeD-mis becomes as thin as 26 nm.

Metallic layer 23 is made of a material having a relatively smalleffective work function because the MIS structure is formed betweenmetallic layer 23 and p-type semiconductor layer 15. Specifically, incase of the effective work function of metallic layer 23 becomes small,the Fermi level of metallic layer 23 is raised. The Fermi level ofmetallic layer 23 is set higher than that of p-type semiconductor layer15.

The thickness of insulating layer 21 is determined based on thecondition that the charge tunneling phenomenon (including both directtunneling and FN tunneling) is generated between p-type semiconductorlayer 15 and metallic layer 23.

For example, in case of insulating layer 21 is made of SiO₂, thethickness of insulating layer 21 is set to the range of 0.1 to 3 nm. Incase of insulating layer 21 is made of SiN or Al₂O₃, the thickness ofinsulating layer 21 is set to the range of 0.1 to 3 nm.

Insulating layer 21 may include an impurity atom or semiconductor/metaldot (quantum dot), which forms the defect level. A fine rectifyingelement (non-ohmic element) that can be formed at a low temperature canbe shrunk by the above structure.

Insulating layer 21 may be formed by a single layer or plural layers. Incase of insulating layer 21 is formed by plural layers, preferably thelayers have different barrier heights or different permittivities.

FIG. 28 illustrates a second example of the structure of the MIS diode.

MIS diode D-mis has a stacked structure of metallic layer 24, insulatinglayer 21, and n-type semiconductor layer 13.

MIS diode D-mis is disposed on electrode layer 12, memory element 17which is the variable resistive element (ReRAM) or the phase-changeelement (PCRAM) is disposed on MIS diode D-mis, and electrode layer 18is disposed on memory element 17.

One of the features of MIS diode D-mis is that the reverse currentcaused by the reverse bias can be sufficiently suppressed during theset/reset operation even if the thickness in the third direction of MISdiode D-mis is set to 100 nm or less.

For example, the thickness in the third direction of MIS diode D-mis isset to the range of 25 nm to 55 nm. For example, metallic layer 24 isset to 10 nm, insulating layer 21 is set to 1 nm, and n-typesemiconductor layer 13 is set to 15 nm, whereby the thickness of MISdiode D-mis becomes 26 nm.

Metallic layer 24 is made of a material having a relatively largeeffective work function because the MIS structure is formed betweenmetallic layer 24 and n-type semiconductor layer 13. Specifically, incase of the effective work function of metallic layer 24 becomes large,the Fermi level of metallic layer 24 is lowered. The Fermi level ofmetallic layer 24 is set lower than that of n-type semiconductor layer13. Alternatively, the p-type semiconductor layer may be used in case ofthe metallic layer is used as a hole supply source.

The thickness of insulating layer 21 is determined based on thecondition that the charge tunneling phenomenon (including both directtunneling and FN tunneling) is generated between metallic layer 24 andn-type semiconductor layer 13.

For example, in case of insulating layer 21 is made of SiO₂, thethickness of insulating layer 21 is set to the range of 0.1 to 3 nm. Incase of insulating layer 21 is made of SiN or Al₂O₃, the thickness ofinsulating layer 21 is set to the range of 0.1 to 3 nm.

Insulating layer 21 may include an impurity atom or semiconductor/metaldot (quantum dot), which forms the defect level. A fine rectifyingelement (non-ohmic element) that can be formed at a low temperature canbe shrunk by the above structure.

Insulating layer 21 may be formed by a single layer or plural layers.When insulating layer 21 is formed by plural layers, preferably thelayers have different barrier heights or different permittivities.

(b) Operation Mechanism

A mechanism of operation of the MIS diode will be described by takingthe structure of FIG. 22 as an example.

FIGS. 23 and 24 illustrate a band structure of the MIS diode.

In case of the insulating layer is disposed between the p-typesemiconductor layer and the metallic layer, the MIS diode has thestructure of FIG. 23 before the band modulation, and has the structureof FIG. 24 after the band modulation.

However, the Fermi level of the metallic layer is higher than that ofp-type semiconductor layer 15. For example, the insulating layer is madeof SiO₂ having a thickness of 1 nm.

In case of a voltage less than 1 V is applied as the forward bias to theMIS diode, as illustrated in FIG. 25, charge movement is generated bythe direct tunneling of the insulating layer (SiO₂), and the currentpassed through the MIS diode increases with increasing forward bias.

In case of a voltage of 1 V or more is applied as the forward bias tothe MIS diode, as illustrated in FIG. 26, charge movement is generatedby the FN tunneling of the insulating layer (SiO₂), and the currentpassed through the MIS diode increases with increasing forward bias.

On the other hand, in case of a voltage less than 1 V is applied as thereverse bias to the MIS diode, as illustrated in FIG. 27, because thecarrier is not tunneling through the insulating layer (SiO₂), thecurrent is not passed through the MIS diode.

For this example, the reverse current of the MIS diode can besufficiently suppressed against the reverse bias of 1 V. At the sametime, a sufficiently large forward current (set/reset current) can beobtained with respect to the forward bias of 1 V.

As the insulating layer is further thickened, the reverse biascharacteristic can be further improved. That is, in applying the reversebias, the reverse current decreases while the breakdown voltageincreases as the insulating layer is thickened.

However, as described above with reference to FIG. 17, because thereverse bias applied to the diode of the resistance change memorygenerally ranges from 0.8 V to 3 V (except for the forming operation),the thickness of the insulating layer constituting the MIS diode rangesfrom 0.1 to 3 nm.

Specifically, the thickness of the insulating layer is determined inconsideration of the forward bias characteristic.

FIG. 29 illustrates a table of effective work functions of metallicmaterials.

As to the relationship between the effective work function and the Fermilevel, the Fermi level is raised in case of the effective work functionbecomes small, and the Fermi level is lowered in case of the effectivework function becomes large.

In the operation, in the MIS diode of FIG. 22, the Fermi level of themetallic layer should be set higher than that of the p-typesemiconductor layer. In the MIS diode of FIG. 28, the Fermi level of themetallic layer should be lower than that of the n-type semiconductorlayer.

Therefore, the metal satisfying the condition mentioned above isselected from the materials of FIG. 29.

(c) Embodiments

FIG. 30 illustrates a first example of the structure of the MIS diode.

The structure of FIG. 30 corresponds to the MIS diode of FIG. 22.

Metallic layer (electrode layer) 23, insulating layer 21, p-typesemiconductor layer 15, and electrode layer 16 are stacked on conductiveline L2(i) extended in the first direction. MIS diode D-mis comprisesmetallic layer 23, insulating layer 21, and p-type semiconductor layer15.

Memory element 17, which is the variable resistive element or thephase-change element, and electrode layer 18 are stacked on electrodelayer 16. Conductive line L3(j) is disposed on electrode layer 18, andextended in the second direction intersecting the first direction. Thatis, electrode layer 12 of FIG. 10 is used as metallic layer 23 of theMIS diode. As a result, the height of memory cell MC can be furtherdecreased.

In MIS diode D-mis, in order to realize the set/reset operation, thereverse current of the MIS diode should be sufficiently suppressed tothe reverse bias applied during the set/reset operation.

Therefore, the thickness in the third direction of MIS diode D-mis isset to the range of 25 nm to 100 nm. For example, metallic layer 23 isset to 10 nm, insulating layer 21 is set to 1 nm, and p-typesemiconductor layer 15 is set to 15 nm, whereby the thickness of MISdiode D-mis becomes 26 nm.

FIG. 31 illustrates a modification of the MIS diode of FIG. 30.

The structure of the MIS diode of the modification differs from thestructure of the MIS diode of FIG. 30 in that intrinsic semiconductorlayer 25 is provided. Specifically, in the modification of FIG. 30,intrinsic semiconductor layer 25 is disposed between insulating layer 21and p-type semiconductor layer 15.

The addition of intrinsic semiconductor layer 25 can further improve thereverse bias characteristic of the MIS diode. That is, the reverse biascharacteristic can be suppressed within the permissible aspect ratio bythe thickened intrinsic semiconductor layer and the thickened insulatingfilm.

In case of insulating layer 21 is thickened, the forward current ishardly passed although the current can be considerably suppressed duringthe reverse bias. Therefore, in case of intrinsic semiconductor layer 25is added while insulating layer 21 is thinned, the forward current canbe increased while the current is suppressed during the reverse bias.

For example, the P-type semiconductor layer is set to 5 nm, theintrinsic semiconductor layer is set to about 60 nm, and the insulatinglayer is made of an extremely-thin (1 nm or less) SiN having a lowbarrier height. Therefore, even if the metal layer is set to 10 nm,because the sum of the layers becomes about 75 nm, the reverse currentcan be suppressed by the effect of the intrinsic semiconductor while thecurrent is increased.

FIG. 32 illustrates a second example of the structure of the MIS diode.

The structure of FIG. 32 corresponds to the MIS diode of FIG. 28.

Electrode layer 12, n-type semiconductor layer 13, insulating layer 21,and metallic layer (electrode layer) 24 are stacked on conductive lineL2(i) extended in the first direction. MIS diode D-mis comprises n-typesemiconductor layer 13, insulating layer 21, and metallic layer 24. Thatis, electrode layer 16 of FIG. 10 is used as metallic layer 24 of theMIS diode. As a result, the height of memory cell MC can be furtherdecreased.

Memory element 17, which is the variable resistive element or thephase-change element, and electrode layer 18 are stacked on MIS diodeD-mis. Conductive line L3(j) is disposed on electrode layer 18, andextended in the second direction intersecting the first direction.

In MIS diode D-mis, in order to realize the set/reset operation, thereverse current of the MIS diode should be sufficiently suppressed tothe reverse bias applied during the set/reset operation.

Therefore, the thickness in the third direction of MIS diode D-mis isset to the range of about 20 nm to about 100 nm. For example, n-typesemiconductor layer 13 is set to 15 nm, insulating layer 21 is set to 1nm, and metallic layer 24 is set to 10 nm, whereby the thickness of MISdiode D-mis becomes 26 nm.

FIG. 33 illustrates a modification of the MIS diode of FIG. 32.

The structure of the MIS diode of the modification differs from thestructure of the MIS diode of FIG. 32 in that intrinsic semiconductorlayer 25 is provided. Specifically, in the modification of FIG. 33,intrinsic semiconductor layer 25 is disposed between insulating layer 21and n-type semiconductor layer 13.

The addition of intrinsic semiconductor layer 25 can further improve thereverse bias characteristic of the MIS diode. That is, the reverse biascharacteristic can be suppressed within the permissible aspect ratio bythe thickened intrinsic semiconductor layer and the thickened insulatingfilm.

In case of insulating layer 21 is thickened, the forward current ishardly passed although the current can be considerably suppressed duringthe reverse bias. Therefore, in case of intrinsic semiconductor layer 25is added while insulating layer 21 is thinned, the forward current canbe increased while the current is suppressed during the reverse bias.

For example, the P-type semiconductor layer is set to 5 nm, intrinsicsemiconductor layer is set to about 60 nm, and the insulating layer ismade of an extremely-thin (1 nm or less) SiN having a low barrierheight. Therefore, even if the metal layer is set to 10 nm, because thesum of the layers becomes about 75 nm, the reverse current can besuppressed by the effect of the intrinsic semiconductor while thecurrent is increased.

(d) Material Example

A material example for the resistance change memory in which the MISdiode is used as the rectifying element will be described.

The p-type semiconductor layer and the n-type semiconductor layer, whichconstitute the MIS diode, are selected from the group of Si, SiGe, SiC,Ge, C, GaAs, an oxide semiconductor, a nitride semiconductor, a carbidesemiconductor, and a sulfide semiconductor.

Preferably, the p-type semiconductor layer (anode layer) is one ofp-type Si, TiO₂, ZrO₂, InZnO_(x), ITO, SnO₂ containing Sb, ZnOcontaining Al, AgSbO₃, InGaZnO₄, and ZnO.SnO₂.

Preferably, the n-type semiconductor layer (cathode layer) is one ofn-type Si, NiO_(x), ZnO, Rh₂O₃, ZnO containing N, and La₂CuO₄.

For example, the insulating layer constituting the MIS diode is selectedfrom the following materials.

A) Oxide

-   -   SiO₂, Al₂O₃, Y₂O₃, La₂O₃, Gd₂O₃, Ce₂O₃, CeO₂, Ta₂O₅, HfO₂, ZrO₂,        TiO₂, HfSiO, HfAlO, ZrSiO, ZrAlO, AlSiO, or a combination        thereof.    -   AB₂O₄

Where A and B are identical or different elements and one of Al, Sc, Ti,V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, or a combination thereof.

For example, Fe₃O₄, FeAl₂O₄, Mn_(1+x)Al_(2−x)O_(4+y),CO_(1+x)Al_(2−x)O_(4+y), and MnO_(x)

-   -   ABO₃

Where A and B are identical or different elements and one of Ai, La, Hf,Ta, W, Re, Os, Ir, Pt, Au, Hg, Tl, Pb, Bi, Ce, Pr, Nd, Pm, Sm, Eu, Gd,Tb, Dy, Ho, Er, Tm, Yb, Lu, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga,Ge, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, In, Sn, or a combinationthereof.

For example, LaAlO₃, SrHfO₃, SrZrO₃, and SrTiO₃

B) Oxynitride

-   -   SiON, AlON, YON, LaON, GdON, CeON, TaON, HfON, ZrON, TiON,        LaAlON, SrHfON, SrZrON, SrTiON, HfSiON, HfAlON, ZrSiON, ZrAlON,        AlSiON, or a combination thereof.    -   A material replaced some of the oxygen elements of the material        in A) Oxide to a nitrogen element.

Particularly, the insulating layer constituting the MIS diode ispreferably selected from the group of SiO₂, SiN, Si₃N₄, Al₂O₃, SiON,HfO₂, HfSiON, Ta₂O₅, TiO₂, and SrTiO₃.

Particularly, for the insulating layer made of an Si-based material suchas SiO₂, SiN, and SiON, each of the oxygen element and the nitrogenelement has a concentration of 1×10¹⁸ atoms/cm³ or more.

The insulating layer includes an insulating layer that contains animpurity atom or semiconductor/metal dot (quantum dot), which forms thedefect level.

The conductive line that acts as the word line/bit line is made of W,WN, Al, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, TiN, WSi_(x), TaSi_(x), PdSi_(x),ErSi_(x), YSi_(x), PtSi_(x), HfSi_(x), NiSi_(x), CoSi_(x), TiSi_(x),VSi_(x), CrSi_(x), MhSi_(x), FeSi_(x), or a combination thereof.

A single metal element or a mixture of metal elements, silicide, oxide,and nitride can be cited as an example of the material for the electrodelayer. Specifically, the electrode layer is made of Pt, Au, Ag, TiAlN,SrRuO, Ru, RuN, Ir, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, TiN, TaN, LaNiO, Al,PtIrO_(x), PtRhO_(x), Rh, TaAlN, SiTiO_(x), WSi_(x), TaSi_(x), PdSi_(x),PtSi_(x), IrSi_(x), ErSi_(x), YSi_(x), HfSi_(x), NiSi_(x), CoSi_(x),TiSi_(x), VSi_(x), CrSi_(x), MnSi_(x), FeSi_(x), or a combinationthereof. The electrode layer may simultaneously have a function as abarrier metallic layer or a bonding layer.

However, the electrode layer includes the metallic layer constitutingthe MIS diode (the electrode layer may also be used as the metalliclayer).

The metallic layer constituting the MIS diode is made of one of thefollowing materials or a combination thereof:

A) A single metal element or a mixture of metal elements,

B) Compound metal that is an oxide, carbide, boride, nitride, orsilicide, and

C) One or a combination of TiN_(x), TiC_(x), TiB_(x), TiSi_(x), TaC_(x),TaB_(x), TaN_(x), WC_(x), WB_(x), W, WSi_(x), TaC_(x), TaB, TaN_(x),TaSi_(x), LaB_(x), LaN_(x), LaSi_(x), HfSi_(x), Hf, YSi_(x), ErSi, NiSi,NiSi_(x), PtSi_(x), PdSi_(x), CoSi_(x), MnSi_(x), CrSi_(x), andFeSi_(x).

For example, the memory element is made of a binary or ternary metaloxide or an organic material.

(e) Effect

In case of the MIS diode is used as the rectifying element of theresistance change memory, the thickness of the rectifying element can bedecreased to ⅓ to ⅕ that of the p-n junction diode and the p-i-n diodewhile maintaining the rectifying characteristic. In other words, in caseof the MIS diode is set to the same thickness as the p-n junction diodeor the p-i-n diode, the reverse current of the MIS diode to which thereverse bias is applied decreases 10³ or more compared with the p-njunction diode or the p-i-n diode, to which the identical reverse biasis applied.

Accordingly, a reduction of the power consumption of the resistancechange memory, improvement in the operating speed, and ease of read canbe realized.

One of the anode layer and cathode layer of the MIS diode is made of ametal while the other is made of a semiconductor, so that the rectifyingcharacteristic can be controlled by adjusting the effective workfunction (Fermi level) of the metal and the Fermi level of thesemiconductor.

Particularly, in case of the cathode layer is made of a metal, in theforward bias, the Fermi level of the metallic layer on theelectron-injection side is relatively raised, and the Fermi level of thep-type semiconductor layer on the electron-reception side is relativelylowered, which allows the rectifying characteristic to be enhanced.

Particularly, in case of the anode layer is made of a metal, in theforward bias, the Fermi level of the metallic layer on theelectron-injection side is relatively raised, and the Fermi level of then-type semiconductor layer on the electron-reception side is relativelylowered, which allows the rectifying characteristic to be enhanced.

In the p-i-n diode, in case of the minimum line width becomes 30 nm orless, unfortunately a variation in characteristic is generated by avariation in impurity concentration of the semiconductor layer. On theother hand, in the MIS diode, the variation in characteristic is reducedbecause one of the anode layer and the cathode layer is made of a metal.

In the MIS diode, one (metallic layer side) of the anode layer and thecathode layer is only considered for the depletion of the semiconductorlayer, which contributes to a thinned diode.

The MIS diode comprises plural insulating layers, and the insulatinglayers differ from each other in the barrier height or the permittivity.Therefore, the on/off-ratio of the MIS diode can be improved by thedifferent barrier heights or permittivities of the insulating layers andthe impurity concentrations of the p-type semiconductor layer and n-typesemiconductor layer.

The on/off-ratio can also be improved by incorporating the trap level (adot or a defect of an impurity or Si) in the single or plural insulatingfilms asymmetrically.

Ultimately, the forward current can be significantly improved byextremely thinning the insulating film. Actually the currentcharacteristic can be improved by the use of an extremely-thininsulating film made of SiO_(x), SiN_(x), TiO_(x), NiO_(x), WO_(x), andthe like, which are formed by natural oxidation or SPA.

D. SMIS Diode

(a) Structure

FIG. 34 illustrates a first example of a structure of the SMIS diode.

SMIS diode D-smis has a stacked structure of p-type semiconductor layer15, insulating layer 21, metallic layer 23, and n-type semiconductorlayer 13.

SMIS diode D-smis is disposed on electrode layer 12, electrode layer 16is disposed on SMIS diode D-smis, memory element 17 which is thevariable resistive element (ReRAM) or the phase-change element (PCRAM)is disposed on electrode layer 16, and electrode layer 18 is disposed onmemory element 17.

The positional relationship between the memory element and therectifying element and the structures of the memory element and therectifying element may be changed in various ways as long as therectifying characteristic of the rectifying element is not lost. Forexample, the memory element and the rectifying element may be formedupside down, the cathode and anode of the rectifying element may bereversed, the electrode layer may be omitted or added, a barrier layerthat suppresses diffusion of the impurity may be added, or a combinationthereof may be performed.

The memory function of utilizing the insulating characteristic changecaused by a trap or ion movement may be added to the insulating layerconstituting the SMIS diode.

One of the features of SMIS diode D-smis is that the reverse currentcaused by the reverse bias can be sufficiently suppressed during theset/reset operation even if the thickness in the third direction of SMISdiode D-smis is set to 100 nm or less.

For example, the thickness in the third direction of SMIS diode D-smisis set to the range of 35 nm to 100 nm. For example, p-typesemiconductor layer 15 is set to 15 nm, insulating layer 21 is set to 1nm, and metallic layer 23 is set to 10 nm, whereby the thickness of SMISdiode D-smis becomes 41 nm.

Metallic layer 23 is made of a material having a relatively smalleffective work function because the MIS structure is formed betweenmetallic layer 23 and p-type semiconductor layer 15. Specifically, whenthe effective work function of metallic layer 23 becomes small, theFermi level of metallic layer 23 is raised. The Fermi level of metalliclayer 23 is set higher than that of p-type semiconductor layer 15.

The thickness of insulating layer 21 is determined based on thecondition that the charge tunneling phenomenon (including both directtunneling and FN tunneling) is generated between p-type semiconductorlayer 15 and metallic layer 23.

For example, in case of insulating layer 21 is made of SiO₂, thethickness of insulating layer 21 is set to the range of 0.1 to 3 nm. Incase of insulating layer 21 is made of SiN or Al₂O₃, the thickness ofinsulating layer 21 is set to the range of 0.1 to 3 nm.

Insulating layer 21 may include an impurity atom or semiconductor/metaldot (quantum dot), which forms the defect level. A fine rectifyingelement (non-ohmic element) that can be formed at a low temperature canbe shrunk by the above structure.

Insulating layer 21 may be formed by a single layer or plural layers. Incase of insulating layer 21 is formed by plural layers, preferably thelayers have different barrier heights or different permittivities.

FIG. 40 illustrates a second example of the structure of the SMIS diode.

SMIS diode D-smis has a stacked structure of p-type semiconductor layer15, metallic layer 24, insulating layer 21, and n-type semiconductorlayer 13.

SMIS diode D-smis is disposed on electrode layer 12, electrode layer 16is disposed on SMIS diode D-smis, memory element 17 which is thevariable resistive element (ReRAM) or the phase-change element (PCRAM)is disposed on electrode layer 16, and electrode layer 18 is disposed onmemory element 17.

One of the features of SMIS diode D-smis is that the reverse currentcaused by the reverse bias can be sufficiently suppressed during theset/reset operation even if the thickness in the third direction of SMISdiode D-smis is set to 100 nm or less.

For example, the thickness in the third direction of SMIS diode D-smisis set to the range of 35 nm to 80 nm. For example, p-type semiconductorlayer 15 is set to 15 nm, metallic layer 24 is set to 10 nm, insulatinglayer 21 is set to 1 nm, and n-type semiconductor layer 13 is set to 15nm, whereby the thickness of SMIS diode D-smis becomes 41 nm.

Metallic layer 24 is made of a material having a relatively largeeffective work function because the MIS structure is formed betweenmetallic layer 24 and n-type semiconductor layer 13. Specifically, incase of the effective work function of metallic layer 24 becomes large,the Fermi level of metallic layer 24 is lowered. The Fermi level ofmetallic layer 24 is set lower than that of n-type semiconductor layer13.

The thickness of insulating layer 21 is determined based on thecondition that the charge tunneling phenomenon (including both directtunneling and FN tunneling) is generated between metallic layer 24 andn-type semiconductor layer 13.

For example, in case of insulating layer 21 is made of SiO₂, thethickness of insulating layer 21 is set to the range of 0.5 to 3 nm. Incase of insulating layer 21 is made of SiN or Al₂O₃, the thickness ofinsulating layer 21 is set to the range of 0.1 to 3 nm.

Insulating layer 21 may include an impurity atom or semiconductor/metaldot (quantum dot), which forms the defect level. A fine rectifyingelement (non-ohmic element) that can be formed at a low temperature canbe shrunk by the above structure.

Insulating layer 21 may be formed by a single layer or plural layers.When insulating layer 21 is formed by plural layers, preferably thelayers have different barrier heights or different permittivities.

(b) Operation Mechanism

An operation mechanism of the SMIS diode will be described by taking thestructure of FIG. 34 as an example.

FIGS. 35 and 36 illustrate a band structure of the SMIS diode.

In case of the insulating layer is disposed between the p-typesemiconductor layer and the metallic layer to bring the n-typesemiconductor layer into contact with the metallic layer, the SMIS diodehas the structure of FIG. 35 before the band modulation, and has thestructure of FIG. 36 after the band modulation.

However, the Fermi level of the metallic layer is higher than that ofp-type semiconductor layer 15. It is assumed that the insulating layeris made of SiO₂ having a thickness of 1 nm.

In case of a voltage less than 1 V is applied as the forward bias to theSMIS diode, as illustrated in FIG. 37, charge movement is generated bythe direct tunneling of the insulating layer (SiO₂), and the currentpassed through the SMIS diode increases with an increasing forward bias.

In case of a voltage of 1 V or more is applied as the forward bias tothe SMIS diode, as illustrated in FIG. 38, charge movement is generatedby the FN tunneling of the insulating layer (SiO₂), and the currentpassed through the SMIS diode increases with an increasing forward bias.

On the other hand, in case of a voltage less than 1 V is applied as thereverse bias to the SMIS diode, as illustrated in FIG. 39, because thecarrier is not tunneling through the insulating layer (SiO₂), thecurrent is not passed through the SMIS diode.

For this example, the reverse current of the SMIS diode can besufficiently suppressed against the reverse bias of 1 V. At the sametime, a sufficiently large forward current (set/reset current) can beobtained with respect to the forward bias of 1 V.

As the insulating layer is further thickened, the reverse biascharacteristic can further be improved. That is, in applying the reversebias, the reverse current decreases while the breakdown voltageincreases as the insulating layer is thickened.

However, as described above with reference to FIG. 17, because thereverse bias applied to the diode of the resistance change memorygenerally ranges from 0.8 V to 3 V (except for the forming operation),the thickness of the insulating layer constituting the SMIS diode rangesfrom 0.1 to 3 nm.

Specifically, the thickness of the insulating layer is determined inconsideration of the forward bias characteristic.

As described above with reference to FIG. 29, the Fermi level of themetallic layer should be higher than that of the p-type semiconductorlayer in the SMIS diode of FIG. 34, and that the Fermi level of themetallic layer should be lower than that of the n-type semiconductorlayer in the SMIS diode of FIG. 40.

Therefore, a metal satisfying the condition is selected from thematerials of FIG. 29.

FIG. 41 illustrates a relationship between a bias direction and acurrent value.

At this point, the MIS/SMIS diode characteristic and the SIS diodecharacteristic are compared to each other.

As to the forward bias characteristic, the forward current passedthrough the MIS/SMIS diode is larger than the forward current passedthrough the SIS diode for the bias of 1 V (point A of FIG. 41) or more.

As to the reverse bias characteristic, the reverse current passedthrough the MIS/SMIS diode is substantially equal to the reverse currentpassed through the SIS diode for the bias of 3 V (point B of FIG. 41) ormore.

Accordingly, in the MIS/SMIS diode, the forward current characteristiccan be improved without degrading the reverse bias characteristic byadjusting the bias applied to the MIS/SMIS diode.

In case of the thickness of the insulating layer is 1 nm or less (exceptzero), the forward bias characteristics and the reverse biascharacteristics of the SIS diode can be approximate to a line-symmetryto a current axis of 1-V characteristics. In this case, the SIS diodemay include an intrinsic semiconductor layer with 10 nm or less. As aresult, the bipolar operation is applied to the resistance change memoryoperating.

(c) Embodiments

FIG. 42 illustrates a first example of the structure of the SMIS diode.

The structure of FIG. 42 corresponds to the SMIS diode of FIG. 34.

Electrode layer 12, n-type semiconductor layer 13, metallic layer 23,insulating layer 21, p-type semiconductor layer 15, and electrode layer16 are stacked on conductive line L2(i) extended in the first direction.SMIS diode D-smis comprises n-type semiconductor layer 13, metalliclayer 23, insulating layer 21, and p-type semiconductor layer 15.

Memory element 17, which is the variable resistive element or thephase-change element, and electrode layer 18 are stacked on electrodelayer 16. Conductive line L3(j) is disposed on electrode layer 18, andextended in the second direction intersecting the first direction.

In SMIS diode D-smis, in order to realize the set/reset operation, thereverse current of the SMIS diode should be sufficiently suppressed thereverse bias applied during the set/reset operation.

Therefore, the thickness in the third direction of SMIS diode D-smis isset to the range of 35 nm to 80 nm. For example, n-type semiconductorlayer 13 is set to 15 nm, metallic layer 23 is set to 10 nm, insulatinglayer 21 is set to 1 nm, and p-type semiconductor layer 15 is set to 15nm, whereby the thickness of SMIS diode D-smis becomes 41 nm.

FIG. 43 illustrates a modification of the SMIS diode of FIG. 42.

The structure of the SMIS diode of the modification differs from thestructure of the SMIS diode of FIG. 42 in that intrinsic semiconductorlayer 25 is provided. Specifically, in the modification of FIG. 43,intrinsic semiconductor layer 25 is disposed between insulating layer 21and p-type semiconductor layer 15.

The addition of intrinsic semiconductor layer 25 can further improve thereverse bias characteristic of the SMIS diode.

FIG. 44 illustrates a second example of the structure of the SMIS diode.

The structure of FIG. 44 corresponds to the SMIS diode of FIG. 40.

Electrode layer 12, n-type semiconductor layer 13, insulating layer 21,metallic layer 24, p-type semiconductor layer 15, and electrode layer 16are stacked on conductive line L2(i) extended in the first direction.SMIS diode D-smis comprises n-type semiconductor layer 13, insulatinglayer 21, metallic layer 24, and p-type semiconductor layer 15.

Memory element 17 which is the variable resistive element or thephase-change element and electrode layer 18 are stacked on electrodelayer 16. Conductive line L3(j) is disposed on electrode layer 18, andextended in the second direction intersecting the first direction.

In SMIS diode D-smis, in order to realize the set/reset operation, thereverse current of the SMIS diode should be sufficiently suppressed tothe reverse bias applied during the set/reset operation.

Therefore, the thickness in the third direction of SMIS diode D-smis isset to the range of 35 nm to 80 nm. For example, n-type semiconductorlayer 13 is set to 15 nm, insulating layer 21 is set to 1 nm, metalliclayer 24 is set to 10 nm, and p-type semiconductor layer 15 is set to 15nm, whereby the thickness of SMIS diode D-smis becomes 41 nm.

FIG. 45 illustrates a modification of the SMIS diode of FIG. 44.

The structure of the SMIS diode of the modification differs from thestructure of the SMIS diode of FIG. 44 in that intrinsic semiconductorlayer 25 is provided. Specifically, in the modification of FIG. 44,intrinsic semiconductor layer 25 is disposed between insulating layer 21and n-type semiconductor layer 13.

The addition of intrinsic semiconductor layer 25 can further improve thereverse bias characteristic of the SMIS diode. That is, the reverse biascharacteristic can be suppressed within the permissible aspect ratio bythe thickened intrinsic semiconductor layer and the thickened insulatingfilm.

In case of insulating layer 21 is thickened, the forward current ishardly passed although the current can be considerably suppressed duringthe reverse bias. Therefore, in case of intrinsic semiconductor layer 25is added while insulating layer 21 is thinned, the forward current canbe gained while the current is suppressed during the reverse bias.

In addition to the MIS diode, a Schottky diode (including an ohmicjunction) may be formed between the semiconductor and the metal tofinely adjust the current characteristic.

For example, the P-type semiconductor layer is set to 5 nm, intrinsicsemiconductor layer is set to about 60 nm, and the insulating layer ismade of the extremely-thin (1 nm or less) SiN having the low barrierheight. Therefore, even if the metal layer is set to 10 nm, because thesum of the layers becomes about 75 nm, the reverse current can besuppressed by the effect of the intrinsic semiconductor while thecurrent is gained.

(d) Material Example

A concrete example for the resistance change memory in which the SMISdiode is used as the rectifying element will be described.

The p-type semiconductor layer and the n-type semiconductor layer, whichconstitute the SMIS diode, are selected from the group of Si, SiGe, SiC,Ge, C, GaAs, an oxide semiconductor, a nitride semiconductor, a carbidesemiconductor, and a sulfide semiconductor.

Preferably, the p-type semiconductor layer (anode layer) is one ofp-type Si, TiO₂, ZrO₂, InZnO_(x), ITO, SnO₂ containing Sb, ZnOcontaining Al, AgSbO₃, InGaZnO₄, and ZnO.SnO₂.

Preferably, the n-type semiconductor layer (cathode layer) is one ofn-type Si, NiO_(x), ZnO, Rh₂O₃, ZnO containing N, and La₂CuO₄.

For example, the insulating layer constituting the SMIS diode isselected from the following materials.

A) Oxide

-   -   SiO₂, Al₂O₃, Y₂O₃, La₂O₃, Gd₂O₃, Ce₂O₃, CeO₂, Ta₂O₅, HfO₂, ZrO₂,        TiO₂, HfSiO, HfAlO, ZrSiO, ZrAlO, AlSiO, or a combination        thereof.    -   AB₂O₄

Where A and B are identical or different elements and one of Al, Sc, Ti,V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, or a combination thereof.

For example, Fe₃O₄, FeAl₂O₄, Mn_(1+x)Al_(2−x)O_(4+y),CO_(1+x)Al_(2−x)O_(4+y), and MnO_(x)

-   -   ABO₃

Where A and B are identical or different elements and one of Ai, La, Hf,Ta, W, Re, Os, Ir, Pt, Au, Hg, Tl, Pb, Bi, Ce, Pr, Nd, Pm, Sm, Eu, Gd,Tb, Dy, Ho, Er, Tm, Yb, Lu, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga,Ge, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, In, Sn, or a combinationthereof.

For example, LaAlO₃, SrHfO₃, SrZrO₃, and SrTiO₃

B) Oxynitride

-   -   SiON, AlON, YON, LaON, GdON, CeON, TaON, HfON, ZrON, TiON,        LaAlON, SrHfON, SrZrON, SrTiON, HfSiON, HfAlON, ZrSiON, ZrAlON,        AlSiON, or a combination thereof.    -   A material replaced some of the oxygen elements of the material        in A) Oxide to a nitrogen element.

Particularly, the insulating layer constituting the SMIS diode ispreferably selected from the group of SiO₂, SiN, Si₃N₄, Al₂O₃, SiON,HfO₂, HfSiON, Ta₂O₅, TiO₂, SrTiO₃, or a combination thereof.

Particularly, for the insulating layer made of an Si-based material suchas SiO₂, SiN, and SiON, each of the oxygen element and the nitrogenelement has a concentration of 1×10¹⁸ atoms/cm³ or more.

The insulating layer includes an insulating layer that contains animpurity atom or semiconductor/metal dot (quantum dot), which forms thedefect level.

The conductive line that acts as the word line/bit line is made of W,WN, Al, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, TiN, WSi_(x), TaSi_(x), PdSi_(x),ErSi_(x), YSi_(x), PtSi_(x), HfSi_(x), NiSi_(x), CoSi_(x), TiSi_(x),VSi_(x), CrSi_(x), MhSi_(x), FeSi_(x), or a combination thereof.

A single metal element or a mixture of metal elements, silicide, oxide,and nitride can be cited as an example of the material for the electrodelayer. Specifically, the electrode layer is made of Pt, Au, Ag, TiAlN,SrRuO, Ru, RuN, Ir, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, TiN, TaN, LaNiO, Al,PtIrO_(x), PtRhO_(x), Rh, TaAlN, SiTiO_(x), WSi_(x), TaSi_(x), PdSi_(x),PtSi_(x), IrSi_(x), ErSi_(x), YSi_(x), HfSi_(x), NiSi_(x), CoSi_(x),TiSi_(x), VSi_(x), CrSi_(x), MnSi_(x), FeSi_(x), or a combinationthereof. The electrode layer may simultaneously have a function as abarrier metallic layer or a bonding layer.

However, the electrode layer includes a metallic layer constituting theSMIS diode (the electrode layer may also be used as the metallic layer).

The metallic layer constituting the SMIS diode is made of one of thefollowing materials or a combination thereof:

A) A single metal element or a mixture of metal elements,

B) Compound metal that is an oxide, carbide, boride, nitride, orsilicide, and

C) One or a combination of TiN_(x), TiC_(x), TiB_(x), TiSi_(x), TaC_(x),TaB_(x), TaN_(x), WC_(x), WB_(x), W, WSi_(x), TaC_(x), TaB, TaN_(x),TaSi_(x), LaB_(x), LaN_(x), LaSi_(x), HfSi_(x), Hf, YSi_(x), ErSi, NiSi,NiSi_(x), PtSi_(x), PdSi_(x), CoSi_(x), MnSi_(x), CrSi_(x), andFeSi_(x).

For example, the memory element is made of a binary or ternary metaloxide or an organic material.

(e) Effect

In case of the SMIS diode is used as the rectifying element of theresistance change memory, the thickness of the rectifying element can bedecreased to ⅓ to ⅕ that of the p-n junction diode and the p-i-n diodewhile the rectifying characteristic is maintained. In other words, incase of the SMIS diode is set to the same thickness as the p-n junctiondiode or the p-i-n diode, the reverse current of the SMIS diode to whichthe reverse bias is applied decreases 10³ or more compared with the p-njunction diode or the p-i-n diode, to which the identical reverse biasis applied.

Accordingly, a reduction of the power consumption of the resistancechange memory, improvement in the operating speed, and ease of read canbe realized.

One of the anode layer and cathode layer of the SMIS diode is made of ametal while the other is made of a semiconductor, so that the rectifyingcharacteristic can be controlled by adjusting the effective workfunction (Fermi level) of the metal and the Fermi level of thesemiconductor.

Particularly, in case of the cathode layer is made of a metal, in theforward bias, the Fermi level of the metallic layer on theelectron-injection side is relatively raised, and the Fermi level of thep-type semiconductor layer on the electron-reception side is relativelylowered, which allows the rectifying characteristic to be enhanced.

Particularly, in case of the anode layer is made of a metal, in theforward bias, the Fermi level of the metallic layer on theelectron-injection side is relatively raised, and the Fermi level of then-type semiconductor layer on the electron-reception side is relativelylowered, which allows the rectifying characteristic to be enhanced.

In the p-i-n diode, in case of the minimum line width becomes 30 nm orless, unfortunately a variation in characteristic is generated by avariation in impurity concentration of the semiconductor layer. On theother hand, in the SMIS diode, the variation in characteristic isreduced because one of the anode layer and the cathode layer is made ofa metal.

In the SMIS diode, consider one (metallic layer side) of the anode layerand the cathode layer is only considered for the depletion of thesemiconductor layer, which contributes to a thinned diode.

In the SMIS diode, because the Schottky barrier is formed by bringingthe semiconductor layer and the metallic layer into contact with eachother, the rectifying characteristic of the Schottky diode can be addedto the rectifying characteristic of the MIS diode. Therefore, therectifying characteristic of the SMIS diode can also be controlled bythe impurity concentration of the semiconductor layer that is in contactwith the metallic layer.

The SMIS diode comprises plural insulating layers, and the insulatinglayers differ from each other in the barrier height or the permittivity.Therefore, the on/off-ratio of the SMIS diode can be improved by thedifferent barrier heights or permittivities of the insulating layers andthe impurity concentrations of the p-type semiconductor layer and n-typesemiconductor layer.

The on/off-ratio can also be improved by incorporating the trap level (adot or a defect of an impurity or Si) in the single or plural insulatingfilms asymmetrically.

Ultimately the forward current can be significantly improved byextremely thinning the insulating film. Actually, the currentcharacteristic can be improved by the use of an extremely-thininsulating film made of SiO_(x), SiN_(x), TiO_(x), NiO_(x), WO_(x), andthe like, which are formed by natural oxidation or SPA.

E. MIM Diode

(a) Structure

FIG. 46 illustrates a structure of an MIM diode.

MIM diode D-mim has a stacked structure of metallic layer 23, insulatinglayers 21A and 21B, and metallic layer 24.

The positional relationship between the memory element and therectifying element and the structures of the memory element and therectifying element may be changed in various ways as long as therectifying characteristic of the rectifying element is not lost. Forexample, the memory element and the rectifying element may be formedupside down, the cathode and anode of the rectifying element may bereversed, the electrode layer may be omitted or added, a barrier layerthat suppresses diffusion of the impurity may be added, or a combinationthereof may be performed.

The memory function of utilizing the insulating characteristic changecaused by a trap or ion movement may be added to the insulating layerconstituting the MIM diode.

The barrier height (or electron affinity) of the material for insulatinglayer 21A differs from the barrier height (or electron affinity) of thematerial for insulating layer 21B. For example, the barrier height ofthe material for insulating layer 21A is higher than that of thematerial for insulating layer 21B.

Preferably, metallic layers 23 and 24 have different effective workfunctions. For example, when the barrier height of the material forinsulating layer 21A is higher than that of the material for insulatinglayer 21B, the effective work function of metallic layer 23 is setlarger than that of metallic layer 24.

At this point, the Fermi level of metallic layer 23 is lower than thatof metallic layer 24.

Memory element 17 which is the variable resistive element (ReRAM) or thephase-change element (PCRAM) is disposed on MIM diode D-mim, andelectrode layer 18 is disposed on memory element 17.

One of the features of MIM diode D-mim is that the reverse currentcaused by the reverse bias can be sufficiently suppressed during theset/reset operation even if the thickness in the third direction of MIMdiode D-mim is set to 100 nm or less.

For example, the thickness in the third direction of MIM diode D-mim isset to the range of 10 nm to 30 nm. For example, metallic layer 23 isset to 10 nm, the sum of thickness of insulating layers 21A and 21B isset to 1 nm, and metallic layer 24 is set to 10 nm, whereby thethickness of MIM diode D-mim becomes 21 nm.

The thickness of insulating layers 21A and 21B is determined based onthe condition that the charge tunneling phenomenon (including bothdirect tunneling and FN tunneling) is generated between two metalliclayers 23 and 24. For example, the sum of thickness of insulating layers21A and 21B is set to the range of 0.5 to 3 nm.

Insulating layers 21A and 21B may include an impurity atom orsemiconductor/metal dot (quantum dot), which forms the defect level. Afine rectifying element (non-ohmic element) that can be formed at a lowtemperature can be shrunk by the above structure.

The number of insulating layers constituting the MIM diode is notlimited to two, and the MIM diode may include at least three insulatinglayers. As illustrated in FIG. 50, three insulating layers, 21A, 21B,and 21C may be disposed between two metallic layers 23 and 24.

Preferably, three insulating layers 21A, 21B, and 21C have differentbarrier heights.

(b) Operation Mechanism

An operation mechanism of the MIM diode will be described by taking thestructure of FIG. 46 as an example.

FIG. 47 illustrates a band structure of the MIM diode.

While the bias is not applied, the barrier height of insulating layer21A is higher than that of insulating layer 21B. For example, insulatinglayer 21A is made of SiO₂ having a thickness of 0.5 nm, and insulatinglayer 21B is made of TiO₂ having a thickness of 1 nm.

In case of the forward bias is applied to the MIM diode, as illustratedin FIG. 48, because electrons are only influenced by the thickness ofinsulating layer 21A, charge movement is generated by the FN tunnelingof insulating layer 21A, and the current passed through the MIM diodeincreases with increasing forward bias.

On the other hand, in case of the reverse bias is applied to the MIMdiode, as illustrated in FIG. 49, because electrons are influenced bythe sum of thickness of insulating layers 21A and 21B, there is notunneling of the carrier through insulating layers 21A and 21B, and thecurrent is not passed through the MIM diode.

For this example, the reverse current of the MIM diode can besufficiently suppressed against the reverse bias. At the same time, asufficiently large forward current (set/reset current) can be obtainedwith respect to the forward bias.

An example of a structure of FIG. 50 will be described.

FIG. 51 illustrates a band structure of the MIM diode.

While the bias is not applied, insulating layers 21A, 21B, and 21Cdiffer from one another in the barrier height. For example, insulatinglayer 21A is made of SiO₂ having a thickness of 0.5 nm, insulating layer21B is made of TiO₂ having a thickness of 1 nm, and insulating layer 21Cis made of SiN having a thickness of 0.5 nm.

In case of the forward bias is applied to the MIM diode, as illustratedin FIG. 52, because electrons are only influenced by the thickness ofinsulating layer 21A, charge movement is generated by the FN tunnelingof insulating layer 21A, and the current passed through the MIM diodeincreases with increasing forward bias.

On the other hand, in case of the reverse bias is applied to the MIMdiode, as illustrated in FIG. 53, because electrons are influenced bythe sum of thickness of the insulating layers 21A, 21B, and 21C, thecarrier is not tunneling through insulating layers 21A, 21B, and 21C,and the current is not passed through the MIM diode.

For this example, the reverse current of the MIM diode can besufficiently suppressed against the reverse bias. At the same time, asufficiently large forward current (set/reset current) can be obtainedwith respect to the forward bias.

(c) Embodiments

FIG. 54 illustrates a structure of the MIM diode.

The structure corresponds to the MIM diode of FIG. 46.

Metallic layer (electrode layer) 23, insulating layers 21A and 21B, andmetallic layer (electrode layer) 24 are stacked on conductive line L2(i)extended in the first direction. MIM diode D-mim comprises metalliclayer 23, insulating layers 21A and 21B, and metallic layer 24.

Memory element 17 which is the variable resistive element or thephase-change element and electrode layer 18 are stacked on MIM diodeD-mim. Conductive line L3(j) is disposed on electrode layer 18, andextended in the second direction intersecting the first direction. Thatis, electrode layer 12 and electrode layer 16 of FIG. 10 are used asmetallic layer 23 and metallic layer 24 of the MIM diode. As a result,the height of memory cell MC can be further decreased.

In MIM diode D-mim, in order to realize the set/reset operation, thereverse current of the MIM diode should be sufficiently suppressed tothe reverse bias applied during the set/reset operation.

Therefore, the thickness in the third direction of MIM diode D-mim isset to the range of 10 nm to 30 nm. For example, metallic layer 23 isset to 10 nm, the sum of thickness of insulating layer 21A and 21B isset to 1 nm, and metallic layer 24 is set to 10 nm, whereby thethickness of MIM diode D-mim becomes 21 nm.

(d) Material Example

A material example for the resistance change memory in which the MIMdiode is used as the rectifying element will be described.

The insulating layers constituting the MIM diode are selected from thefollowing materials.

A) Oxide

-   -   SiO₂, Al₂O₃, Y₂O₃, La₂O₃, Gd₂O₃, Ce₂O₃, CeO₂, Ta₂O₅, HfO₂, ZrO₂,        TiO₂, HfSiO, HfAlO, ZrSiO, ZrAlO, AlSiO, or a combination        thereof.    -   AB₂O₄

Where A and B are identical or different elements and one of Al, Sc, Ti,V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, or a combination thereof.

For example, Fe₃O₄, FeAl₂O₄, Mn_(1+x)Al_(2−x)O_(4+y),CO_(1+x)Al_(2−x)O_(4+y), and MnO_(x)

-   -   ABO₃

Where A and B are identical or different elements and one of Ai, La, Hf,Ta, W, Re, Os, Ir, Pt, Au, Hg, Ti, Pb, Bi, Ce, Pr, Nd, Pm, Sm, Eu, Gd,Tb, Dy, Ho, Er, Tm, Yb, Lu, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga,Ge, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, In, Sn, or a combinationthereof.

For example, LaAlO₃, SrHfO₃, SrZrO₃, and SrTiO₃

B) Oxynitride

-   -   SiON, AlON, YON, LaON, GdON, CeON, TaON, HfON, ZrON, TiON,        LaAlON, SrHfON, SrZrON, SrTiON, HfSiON, HfAlON, ZrSiON, ZrAlON,        AlSiON, or a combination thereof.    -   A material replaced some of the oxygen elements of the material        in A) Oxide to a nitrogen element.

Particularly, the insulating layer constituting the MIM diode ispreferably selected from the group of SiO₂, SiN, Si₃N₄, Al₂O₃, SiON,HfO₂, HfSiON, Ta₂O₅, TiO₂, SrTiO₃, or a combination thereof.

Particularly, for the insulating layer made of an Si-based material suchas SiO₂, SiN, and SiON, each of the oxygen element and the nitrogenelement has a concentration of 1×10¹⁸ atoms/cm³ or more. However,preferably the insulating layers have barrier heights that are differentfrom one another.

The insulating layer includes a material that contains an impurity atomor semiconductor/metal dot (quantum dot), which forms the defect level.

The conductive line that acts as the word line/bit line is made of W,WN, Al, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, TiN, WSi_(x), TaSi_(x), PdSi_(x),ErSi_(x), YSi_(x), PtSi_(x), HfSi_(x), NiSi_(x), CoSi_(x), TiSi_(x),VSi_(x), CrSi_(x), MhSi_(x), FeSi_(x), or a combination thereof.

A single metal element or a mixture of metal elements, silicide, oxide,and nitride can be cited as an example of the material for the electrodelayer. Specifically, the electrode layer is made of Pt, Au, Ag, TiAlN,SrRuO, Ru, RuN, Ir, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, TiN, TaN, LaNiO, Al,PtIrO_(x), PtRhO_(x), Rh, TaAlN, SiTiO_(x), WSi_(x), TaSi_(x), PdSi_(x),PtSi_(x), IrSi_(x), ErSi_(x), YSi_(x), HfSi_(x), NiSi_(x), CoSi_(x),TiSi_(x), VSi_(x), CrSi_(x), MnSi_(x), FeSi_(x), or a combinationthereof. The electrode layer may simultaneously have a function as abarrier metallic layer or a bonding layer.

However, the electrode layer includes the metallic layer constitutingthe MIM diode (the electrode layer may also be used as the metalliclayer).

The two metallic layers constituting the MIM diode are made of one ofthe following materials:

A) A single metal element,

B) Compound metal that is an oxide, carbide, boride, nitride orsilicide, and

C) TiN_(x), TiC_(x), TiB_(x), TiSi_(x), TaC_(x), TaB_(x), TaN_(x),WC_(x), WB_(x), W, WSi_(x), TaC_(x), TaB_(x), TaN_(x), TaSi_(x),HfSi_(x), Hf, YSi_(x), ErSi_(x).

However, the two metallic layers have different effective workfunctions.

For example, when one of the two metallic layers is made of a materialselected from one of ErSi_(x), HfSi_(x), YSi_(x), TaC_(x), TaN_(x),TiN_(x), TiC_(x), TiB_(x), LaB_(x), La, LaN_(x), or a combinationthereof which have a small effective work function, preferably the otheris made of a material selected from one of WN_(x), W, WB_(x), WC_(x),Pt, PtSi_(x), Pd, PdSi_(x), Ir, and IrSi_(x), or a combination thereofwhich have a large effective work function.

For example, the memory element is made of a binary or ternary metaloxide.

(e) Effect

In case of the MIM diode is used as the rectifying element of theresistance change memory, the thickness of the rectifying element can bedecreased to ⅕ to 1/10 that of the p-n junction diode and the p-i-ndiode while the rectifying characteristic is maintained. In other words,in case of the MIM diode is set to the same thickness as the p-njunction diode or the p-i-n diode, the reverse current of the MIS diodeto which the reverse bias is applied decreases 10³ or more compared withthe p-n junction diode or p-i-n diode, to which an identical reversebias is applied.

Accordingly, a reduction of the power consumption of the resistancechange memory, improvement in the operating speed, and ease of read canbe realized.

Both the anode layer and cathode layer of the MIM diode are made of ametal, so that the rectifying characteristic can be controlled byadjusting the effective work function (Fermi level) of the metal.

In the p-i-n diode, when the minimum line width becomes 30 nm or less,unfortunately a variation in characteristic is generated by thevariation in impurity concentration of the semiconductor layer. On theother hand, in the MIM diode, the variation in characteristic is reducedbecause both the anode layer and the cathode layer are made of a metal.

In the MIM diode, the depletion of the semiconductor layer is notconsidered, which contributes to a thinned diode.

The MIM diode comprises plural insulating layers, and the insulatinglayers differ from each other in the barrier height or the permittivity.Therefore, the on/off-ratio of the MIS diode can be improved by thedifferent barrier heights or permittivities of the insulating layers.

The on/off-ratio can also be improved by incorporating the trap level (adot or a defect of an impurity or Si) in the single or plural insulatingfilms asymmetrically.

Ultimately, the forward current can be significantly improved byextremely thinning the insulating film. In practice, the currentcharacteristic can be improved by the use of an extremely-thininsulating film made of SiO_(x), SiN_(x), TiO_(x), NiO_(x), WO_(x), andthe like, which are formed by natural oxidation or SPA.

3. APPLICATION EXAMPLE

The resistance change memory of the embodiment has a high potential as anext-generation universal memory that replaces the current memories,such as the magnetic memory, the NAND flash memory, and the dynamicrandom access memory, which are used in commercially available products.

Therefore, for example, the invention may be applied to a file memory inwhich the data can randomly be written at high speed, a mobile terminalthat can download data at high speed, a portable player that candownload data at high speed, a semiconductor memory for broadcastingequipment, a drive recorder, a home video, a large-capacity buffermemory for communication, and a semiconductor memory for a securitycamera.

4. CONCLUSION

According to the invention, the rectifying element can be sufficientlythinned while satisfying the rectifying element characteristic requiredfor the resistance change memory. The resistance change memory of theinvention has a large advantage as a next-generation universal memory.

Additional advantages and modifications will readily occur to thoseskilled in the art. Therefore, the invention in its broader aspects isnot limited to the specific details and representative embodiments shownand described herein. Accordingly, various modifications may be madewithout departing from the spirit or scope of the general inventiveconcept as defined by the appended claims and their equivalents.

1. A resistance change memory comprising: a first conductive lineextending in a first direction; a second conductive line extending in asecond direction which is crossed to the first direction; a cell unitincluding a memory element and a rectifying element connected in seriesbetween the first and second conductive lines; and a control circuitwhich is connected to both of the first and second conductive lines,wherein the control circuit controls a voltage to change a resistance ofthe memory element between first and second values reversibly, whereinthe rectifying element is a diode including an anode layer, a cathodelayer and an insulating layer therebetween.
 2. The memory according toclaim 1, wherein the diode is an SIS diode in which both the anode layerand the cathode layer are made of a semiconductor layer.
 3. The memoryaccording to claim 2, wherein the insulating layer is one selected fromthe group of SiO₂, SiN, Si₃N₄, Al₂O₃, SiON, HfO₂, HfSiON, Ta₂O₅, TiO₂,and SrTiO₃.
 4. The memory according to claim 2, wherein the insulatinglayer includes one of an impurity atom, a semiconductor dot, and a metaldot, which form a defect level.
 5. The memory according to claim 2,wherein the semiconductor layer is one selected from the group of Si,SiGe, SiC, Ge, C, GaAs, oxide semiconductor, nitride semiconductor,carbide semiconductor, and sulfide semiconductor.
 6. The memoryaccording to claim 2, wherein the anode layer is one of p-type Si, TiO₂,ZrO₂, InZnO_(x), ITO, SnO₂ containing Sb, ZnO containing Al, AgSbO₃,InGaZnO₄, and ZnO.SnO₂, and the cathode layer is one of n-type Si,NiO_(x), ZnO, Rh₂O₃, ZnO containing N, and La₂CuO₄.
 7. The memoryaccording to claim 2, wherein at least one of the anode layer and thecathode layer has an intrinsic semiconductor layer in a region being incontact with the insulating layer.
 8. The memory according to claim 1,wherein the diode is an MIS diode in which one of the anode layer andthe cathode layer is made of a metal while the other is made of asemiconductor.
 9. The memory according to claim 8, wherein theinsulating layer is one selected from the group of SiO₂, SiN, Si₃N₄,Al₂O₃, SiON, HfO₂, HfSiON, Ta₂O₅, TiO₂, and SrTiO₃.
 10. The memoryaccording to claim 8, wherein the insulating layer includes one of animpurity atom, a semiconductor dot, and a metal dot, which form a defectlevel.
 11. The memory according to claim 8, wherein the metallic layeris made of one of A) a single element, B) compound metal that is anoxide, carbide, boride, nitride, or silicide, and C) TiN_(x), TiC_(x),TiB_(x), TiSi_(x), TaC_(x), TaB_(x), TaN_(x), WC_(x), WB_(x), W,WSi_(x), TaC_(x), TaB_(x), TaN_(x), TaSi_(x), HfSi_(x), Hf, YSi_(x), orErSi_(x).
 12. The memory according to claim 8, wherein the semiconductorlayer is one selected from the group of Si, SiGe, SiC, Ge, C, GaAs,oxide semiconductor, nitride semiconductor, carbide semiconductor, andsulfide semiconductor.
 13. The memory according to claim 8, wherein thesemiconductor layer has an intrinsic semiconductor layer in a regionbeing in contact with the insulating layer.
 14. The memory according toclaim 8, wherein the anode layer is one of p-type Si, TiO₂, ZrO₂,InZnO_(x), ITO, SnO₂ containing Sb, ZnO containing Al, AgSbO₃, InGaZnO₄,and ZnO.SnO₂ when the semiconductor layer is the anode layer, and thecathode layer is one of n-type Si, NiO_(x), ZnO, Rh₂O₃, ZnO containingN, and La₂CuO₄ when the semiconductor layer is the cathode layer. 15.The memory according to claim 8, further comprising a semiconductorlayer which is disposed on a side opposite to the insulating layer sideof the metallic layer.
 16. The memory according to claim 1, wherein thediode is an MIM diode in which both the anode layer and the cathodelayer are made of a metal.
 17. The memory according to claim 16, whereinthe insulating layer is one selected from the group of SiO₂, SiN, Si₃N₄,Al₂O₃, SiON, HfO₂, HfSiON, Ta₂O₅, TiO₂, and SrTiO₃.
 18. The memoryaccording to claim 16, wherein the insulating layer includes one of animpurity atom, a semiconductor dot, and a metal dot, which form a defectlevel.
 19. The memory according to claim 16, wherein the insulatinglayer comprises a first layer located on the anode layer side and asecond layer located on the cathode layer side, and a barrier height ofa material for the second layer differs from a barrier height of amaterial for the first layer.
 20. The memory according to claim 16,wherein the metallic layer is made of one of A) a single element, B)compound metal that is an oxide, carbide, boride, nitride, or silicide,and C) TiN_(x), TiC_(x), TiB_(x), TiSi_(x), TaC_(x), TaB_(x), TaN_(x),WC_(x), WB_(x), W, WSi_(x), TaC_(x), TaB_(x), TaN_(x), TaSi_(x),HfSi_(x), Hf, YSi_(x), or ErSi_(x).